On Mon, 7 Jul 2025 at 18:25, Eric Auger <eric.au...@redhat.com> wrote: > > Hi Peter, > > On 7/7/25 6:10 PM, Peter Maydell wrote: > > The GICD_TYPER2 register is new for GICv4.1. As an ID register, we > > migrate it so that on the destination the kernel can check that the > > destination supports the same configuration that the source system > > had. This avoids confusing behaviour if the user tries to migrate a > > VM from a GICv3 system to a GICv4.1 system or vice-versa. (In > > practice the inability to migrate between different CPU types > > probably already prevented this.) > > > > Note that older kernels pre-dating GICv4.1 support in the KVM GIC > > will just ignore whatever userspace writes to GICD_TYPER2, so > > migration where the destination is one of those kernels won't have > > this safety-check. > > > > (The reporting of a mismatch will be a bit clunky, because this > > file currently uses error_abort for all failures to write the > > data to the kernel. Ideally we would fix this by making them > > propagate the failure information back up to the post_load hook > > return value, to cause a migration failure.)
> > diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c > > index 3be3bf6c28d..0302beb0c07 100644 > > --- a/hw/intc/arm_gicv3_kvm.c > > +++ b/hw/intc/arm_gicv3_kvm.c > > @@ -332,6 +332,9 @@ static void kvm_arm_gicv3_put(GICv3State *s) > > kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false); > > redist_typer = ((uint64_t)regh << 32) | regl; > > > > + reg = s->gicd_typer2; > > + kvm_gicd_access(s, GICD_TYPER2, ®, true); > > + > I don't know if there is any rationale about the access order. I see > most of the dist reg accesses are done below in the function after rdist > ones, although the GICD_CTLR is also here. If there is a rationale a > comment may be useful to avoid another dev to do something wrong. I > remember that for the ITS for instance some speicifc ordering needed to > be enforced. I think in general we have tried to put in comments to note where the ordering matters. (Though I do suspect the GICD_CTLR write may be early because we need to write the enable bit before doing anything else -- if that's true, we failed to document it.) In this case I just put this one at the top because "bail out early if the config is wrong" seemed better than doing it late. But it doesn't matter and it's probably more sensible to do it with the other GICD registers. A comment that we only write this ID register to validate the config would also help. > While at it you can also fix the missing bracket at > /* Distributor state (shared between all CPUs */ Sure. thanks -- PMM
