This series adds support for all FEAT_MEC registers and cache instructions to the arm64 max CPU.
It includes the FEAT_MEC registers and cache maintenance instructions, but does not modify the translation regimes to support the MECIDs, so no encryption is supported yet. However, most software stacks that rely on FEAT_MEC should work properly at this point. I'm currently exploring possibilities to support FEAT_MEC encryption (or obfuscation, for testing purposes) in QEMU for the various translation regimes on arm64, hence the encryption part of FEAT_MEC will be contributed later and is not targeted for QEMU 10.1. Cheers, Gustavo Gustavo Romero (6): target/arm: Add the MECEn SCR_EL3 bit target/arm: Add FEAT_MEC registers target/arm: Add FEAT_SCTLR2 target/arm: Add FEAT_TCR2 target/arm: Implement FEAT_MEC cache instructions target/arm: Advertise FEAT_MEC in cpu max docs/system/arm/emulation.rst | 5 + target/arm/cpu-features.h | 15 +++ target/arm/cpu.h | 29 ++++ target/arm/helper.c | 242 ++++++++++++++++++++++++++++++++++ target/arm/internals.h | 20 +++ target/arm/tcg/cpu64.c | 3 + 6 files changed, 314 insertions(+) -- 2.34.1
