On 7/9/25 12:03, Gustavo Romero wrote:
Add all FEAT_MEC registers.
To work properly, FEAT_MEC also depends on FEAT_SCTLR2 and FEAT_TCR2,
which are not implemented in this commit. The bits in SCTLR2 and TCR2
control which translation regimes use MECIDs, and determine which MECID
is selected.
FEAT_MEC also requires two new cache management instructions, not
included in this commit, that will be implemented in subsequent commits.
Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org>
---
target/arm/cpu-features.h | 5 +++
target/arm/cpu.h | 11 ++++++
target/arm/helper.c | 70 +++++++++++++++++++++++++++++++++++++++
3 files changed, 86 insertions(+)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 5876162428..552d8757b7 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -594,6 +594,11 @@ static inline bool isar_feature_aa64_hbc(const
ARMISARegisters *id)
return FIELD_EX64_IDREG(id, ID_AA64ISAR2, BC) != 0;
}
+static inline bool isar_feature_aa64_mec(const ARMISARegisters *id)
+{
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR3, MEC) != 0;
+}
+
static inline bool isar_feature_aa64_mops(const ARMISARegisters *id)
{
return FIELD_EX64_IDREG(id, ID_AA64ISAR2, MOPS);
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 0f64c7b163..a93eebe077 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -576,6 +576,15 @@ typedef struct CPUArchState {
/* NV2 register */
uint64_t vncr_el2;
+
+ /* MEC registers */
+ uint64_t mecid_p0_el2;
+ uint64_t mecid_a0_el2;
+ uint64_t mecid_p1_el2;
+ uint64_t mecid_a1_el2;
+ uint64_t mecid_rl_a_el3;
+ uint64_t vmecid_p_el2;
+ uint64_t vmecid_a_el2;
} cp15;
struct {
@@ -2424,6 +2433,8 @@ FIELD(MFAR, FPA, 12, 40)
FIELD(MFAR, NSE, 62, 1)
FIELD(MFAR, NS, 63, 1)
+#define MECID_WIDTH 16
This could go in internals.h.
Otherwise,
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
