On Wed, Jul 16, 2025 at 11:54:01AM +0200, Luc Michel wrote:
> Refactor the CRL device creation using the VersalMap structure. The
> connections to the RPU CPUs are temporarily removed and will be
> reintroduced with next refactoring commits.
>
> Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
> ---
> include/hw/arm/xlnx-versal.h | 3 ---
> hw/arm/xlnx-versal.c | 36 +++++++++++++++++++-----------------
> 2 files changed, 19 insertions(+), 20 deletions(-)
>
> diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
> index 5a685aea6d4..d3ce13e69de 100644
> --- a/include/hw/arm/xlnx-versal.h
> +++ b/include/hw/arm/xlnx-versal.h
> @@ -15,11 +15,10 @@
>
> #include "hw/sysbus.h"
> #include "hw/cpu/cluster.h"
> #include "hw/intc/arm_gicv3.h"
> #include "qom/object.h"
> -#include "hw/misc/xlnx-versal-crl.h"
> #include "net/can_emu.h"
> #include "target/arm/cpu.h"
> #include "hw/arm/xlnx-versal-version.h"
>
> #define TYPE_XLNX_VERSAL_BASE "xlnx-versal-base"
> @@ -69,12 +68,10 @@ struct Versal {
> MemoryRegion mr_ps_alias;
>
> CPUClusterState cluster;
> ARMCPU cpu[XLNX_VERSAL_NR_RCPUS];
> } rpu;
> -
> - XlnxVersalCRL crl;
> } lpd;
>
> struct {
> uint32_t clk_25mhz;
> uint32_t clk_125mhz;
> diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
> index 2128dbbad92..ff55ec62301 100644
> --- a/hw/arm/xlnx-versal.c
> +++ b/hw/arm/xlnx-versal.c
> @@ -40,10 +40,11 @@
> #include "hw/misc/xlnx-versal-trng.h"
> #include "hw/rtc/xlnx-zynqmp-rtc.h"
> #include "hw/misc/xlnx-versal-cfu.h"
> #include "hw/misc/xlnx-versal-cframe-reg.h"
> #include "hw/or-irq.h"
> +#include "hw/misc/xlnx-versal-crl.h"
>
> #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
> #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
> #define GEM_REVISION 0x40070106
>
> @@ -149,10 +150,12 @@ typedef struct VersalMap {
> size_t num_cframe;
> struct VersalCfuCframeCfg {
> uint32_t blktype_frames[7];
> } cframe_cfg[15];
> } cfu;
> +
> + VersalSimplePeriphMap crl;
> } VersalMap;
>
> static const VersalMap VERSAL_MAP = {
> .uart[0] = { 0xff000000, 18 },
> .uart[1] = { 0xff010000, 19 },
> @@ -213,10 +216,12 @@ static const VersalMap VERSAL_MAP = {
> { { 38498, 3841, 15361, 13, 7, 3, 1 } },
> { { 38498, 3841, 15361, 13, 7, 3, 1 } },
> { { 38498, 3841, 15361, 13, 7, 3, 1 } },
> },
> },
> +
> + .crl = { 0xff5e0000, 10 },
> };
>
> static const VersalMap *VERSION_TO_MAP[] = {
> [VERSAL_VER_VERSAL] = &VERSAL_MAP,
> };
> @@ -1106,31 +1111,28 @@ static void versal_create_cfu(Versal *s, const struct
> VersalCfuMap *map)
> sysbus_realize_and_unref(sbd, &error_fatal);
> memory_region_add_subregion(&s->mr_ps, map->cfu_sfr,
> sysbus_mmio_get_region(sbd, 0));
> }
>
> -static void versal_create_crl(Versal *s, qemu_irq *pic)
> +static inline void versal_create_crl(Versal *s)
> {
> - SysBusDevice *sbd;
> - int i;
> + const VersalMap *map;
> + const char *crl_class;
> + DeviceState *dev;
>
> - object_initialize_child(OBJECT(s), "crl", &s->lpd.crl,
> - TYPE_XLNX_VERSAL_CRL);
> - sbd = SYS_BUS_DEVICE(&s->lpd.crl);
> + map = versal_get_map(s);
>
> - for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) {
> - g_autofree gchar *name = g_strdup_printf("cpu_r5[%d]", i);
> + crl_class = TYPE_XLNX_VERSAL_CRL;
> + dev = qdev_new(crl_class);
> + object_property_add_child(OBJECT(s), "crl", OBJECT(dev));
>
> - object_property_set_link(OBJECT(&s->lpd.crl),
> - name, OBJECT(&s->lpd.rpu.cpu[i]),
> - &error_abort);
> - }
> + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_abort);
>
> - sysbus_realize(sbd, &error_fatal);
> - memory_region_add_subregion(&s->mr_ps, MM_CRL,
> - sysbus_mmio_get_region(sbd, 0));
> - sysbus_connect_irq(sbd, 0, pic[VERSAL_CRL_IRQ]);
> + memory_region_add_subregion(&s->mr_ps, map->crl.addr,
> + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
> 0));
> +
> + versal_sysbus_connect_irq(s, SYS_BUS_DEVICE(dev), 0, map->crl.irq);
> }
>
> /* This takes the board allocated linear DDR memory and creates aliases
> * for each split DDR range/aperture on the Versal address map.
> */
> @@ -1327,12 +1329,12 @@ static void versal_realize(DeviceState *dev, Error
> **errp)
>
> versal_create_bbram(s, &map->bbram);
> versal_create_trng(s, &map->trng);
> versal_create_rtc(s, &map->rtc);
> versal_create_cfu(s, &map->cfu);
> + versal_create_crl(s);
>
> - versal_create_crl(s, pic);
> versal_map_ddr(s);
> versal_unimp(s);
>
> /* Create the On Chip Memory (OCM). */
> memory_region_init_ram(&s->lpd.mr_ocm, OBJECT(s), "ocm",
> --
> 2.50.0
>
