On Wed, Jul 16, 2025 at 11:54:17AM +0200, Luc Michel wrote:
> Use the bsa.h header for ARM timer and maintainance IRQ indices instead
> of redefining our owns.
> 
> Signed-off-by: Luc Michel <luc.mic...@amd.com>

Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>

> ---
>  include/hw/arm/xlnx-versal.h |  6 ------
>  hw/arm/xlnx-versal.c         | 28 +++++++++++++++++-----------
>  2 files changed, 17 insertions(+), 17 deletions(-)
> 
> diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
> index ffa7801b30f..3be9f0a5550 100644
> --- a/include/hw/arm/xlnx-versal.h
> +++ b/include/hw/arm/xlnx-versal.h
> @@ -84,16 +84,10 @@ int versal_get_num_can(VersalVersion version);
>  int versal_get_num_sdhci(VersalVersion version);
>  
>  /* Memory-map and IRQ definitions. Copied a subset from
>   * auto-generated files.  */
>  
> -#define VERSAL_GIC_MAINT_IRQ        9
> -#define VERSAL_TIMER_VIRT_IRQ       11
> -#define VERSAL_TIMER_S_EL1_IRQ      13
> -#define VERSAL_TIMER_NS_EL1_IRQ     14
> -#define VERSAL_TIMER_NS_EL2_IRQ     10
> -
>  #define VERSAL_CRL_IRQ             10
>  #define VERSAL_UART0_IRQ_0         18
>  #define VERSAL_UART1_IRQ_0         19
>  #define VERSAL_CANFD0_IRQ_0        20
>  #define VERSAL_CANFD1_IRQ_0        21
> diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
> index 796b4911a02..c513d28c8d4 100644
> --- a/hw/arm/xlnx-versal.c
> +++ b/hw/arm/xlnx-versal.c
> @@ -47,10 +47,11 @@
>  #include "hw/intc/arm_gicv3_its_common.h"
>  #include "hw/intc/arm_gic.h"
>  #include "hw/core/split-irq.h"
>  #include "target/arm/cpu.h"
>  #include "hw/cpu/cluster.h"
> +#include "hw/arm/bsa.h"
>  
>  #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
>  #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
>  #define GEM_REVISION        0x40070106
>  
> @@ -674,11 +675,12 @@ static DeviceState *versal_create_gic(Versal *s,
>          }
>  
>          qemu_fdt_setprop_cell(s->cfg.fdt, node, "phandle", s->phandle.gic);
>          qemu_fdt_setprop_cell(s->cfg.fdt, node, "#interrupt-cells", 3);
>          qemu_fdt_setprop_cells(s->cfg.fdt, node, "interrupts",
> -                               GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ,
> +                               GIC_FDT_IRQ_TYPE_PPI,
> +                               INTID_TO_PPI(ARCH_GIC_MAINT_IRQ),
>                                 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
>          qemu_fdt_setprop(s->cfg.fdt, node, "interrupt-controller", NULL, 0);
>      }
>  
>      versal_create_gic_its(s, map, dev, mr, node);
> @@ -699,14 +701,14 @@ static void connect_gic_to_cpu(const 
> VersalCpuClusterMap *map,
>      /*
>       * Mapping from the output timer irq lines from the CPU to the
>       * GIC PPI inputs.
>       */
>      const int timer_irq[] = {
> -        [GTIMER_PHYS] = VERSAL_TIMER_NS_EL1_IRQ,
> -        [GTIMER_VIRT] = VERSAL_TIMER_VIRT_IRQ,
> -        [GTIMER_HYP]  = VERSAL_TIMER_NS_EL2_IRQ,
> -        [GTIMER_SEC]  = VERSAL_TIMER_S_EL1_IRQ,
> +        [GTIMER_PHYS] = INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ),
> +        [GTIMER_VIRT] = INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ),
> +        [GTIMER_HYP]  = INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ),
> +        [GTIMER_SEC]  = INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ),
>      };
>  
>      has_gtimer = arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_GENERIC_TIMER);
>  
>      if (has_gtimer) {
> @@ -717,13 +719,13 @@ static void connect_gic_to_cpu(const 
> VersalCpuClusterMap *map,
>          }
>      }
>  
>      if (map->gic.version == 3) {
>          qemu_irq maint_irq;
> +        int maint_idx = ppibase + INTID_TO_PPI(ARCH_GIC_MAINT_IRQ);
>  
> -        maint_irq = qdev_get_gpio_in(gic,
> -                                     ppibase + VERSAL_GIC_MAINT_IRQ);
> +        maint_irq = qdev_get_gpio_in(gic, maint_idx);
>          qdev_connect_gpio_out_named(cpu, "gicv3-maintenance-interrupt",
>                                      0, maint_irq);
>      }
>  
>      sysbus_connect_irq(sbd, idx, qdev_get_gpio_in(cpu, ARM_CPU_IRQ));
> @@ -845,17 +847,21 @@ static void versal_create_cpu_cluster(Versal *s, const 
> VersalCpuClusterMap *map)
>  
>      has_gtimer = arm_feature(&ARM_CPU(cpus[0])->env, 
> ARM_FEATURE_GENERIC_TIMER);
>      if (map->dtb_expose && has_gtimer) {
>          qemu_fdt_add_subnode(s->cfg.fdt, "/timer");
>          qemu_fdt_setprop_cells(s->cfg.fdt, "/timer", "interrupts",
> -                               GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_S_EL1_IRQ,
> +                               GIC_FDT_IRQ_TYPE_PPI,
> +                               INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ),
>                                 GIC_FDT_IRQ_FLAGS_LEVEL_HI,
> -                               GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL1_IRQ,
> +                               GIC_FDT_IRQ_TYPE_PPI,
> +                               INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ),
>                                 GIC_FDT_IRQ_FLAGS_LEVEL_HI,
> -                               GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_VIRT_IRQ,
> +                               GIC_FDT_IRQ_TYPE_PPI,
> +                               INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ),
>                                 GIC_FDT_IRQ_FLAGS_LEVEL_HI,
> -                               GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL2_IRQ,
> +                               GIC_FDT_IRQ_TYPE_PPI,
> +                               INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ),
>                                 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
>          qemu_fdt_setprop(s->cfg.fdt, "/timer", "compatible",
>                           compatible, sizeof(compatible));
>      }
>  }
> -- 
> 2.50.0
> 

Reply via email to