Jonathan Cameron <jonathan.came...@huawei.com> writes:
> On Tue, 5 Aug 2025 22:57:05 -0700
> Davidlohr Bueso <d...@stgolabs.net> wrote:
>
>> As with the link speed and width training, have ad-hoc property for
>> setting the flit mode and allow CXL components to make use of it.
>>
>> For the CXL root port and dsp cases, always report flit mode but
>> the actual value after 'training' will depend on the downstream
>> device configuration.
>>
>> Suggested-by: Jonathan Cameron <jonathan.came...@huawei.com>
>> Signed-off-by: Davidlohr Bueso <d...@stgolabs.net>
> Hi Davidlohr,
>
> This looks a bit like an interface that evolved, but in the end
> you seem to have something that is a simple boolean property.
> As such you can avoid a fair bit of complexity.
> Look for disable-acs for an example.
>
>
> I don't know if it is desirable to make it an explicit type or not,
> but my gut says boolean is fine here.
>
> +CC A few potentially relevant people to answer that question more
> definitively.
[...]
>> diff --git a/qapi/common.json b/qapi/common.json
>> index 0e3a0bbbfb0b..da047fbf874f 100644
>> --- a/qapi/common.json
>> +++ b/qapi/common.json
>> @@ -140,6 +140,20 @@
>> { 'enum': 'PCIELinkWidth',
>> 'data': [ '1', '2', '4', '8', '12', '16', '32' ] }
>>
>
> Hmm. Not sure why these are here rather than pci.json.
Pretty sure there was a good reason back then. Less sure there is a
good reason now :)
>> +##
>> +# @PCIELinkFlit:
>> +#
>> +# An enumeration of PCIe link FLIT mode
>
> Bit odd having an enumeration for 'on' vs 'off'
Indeed. Please stick to bool.
>> +#
>> +# @off: the link is not operating in FLIT mode
>> +#
>> +# @on: each FLIT is a fixed 256 bytes in size
>> +#
>> +# Since: 10.0
>
> That was a while back.
>
>> +##
>> +{ 'enum': 'PCIELinkFlit',
>> + 'data': [ 'off', 'on'] }
>> +
>> ##
>> # @HostMemPolicy:
>> #
