Hardware page table walk (PTW for short) is one feature supported in
Loongson 3C6000 system. With hardware PTW supported, if there is an TLB
miss, hardware will take PTW and fill it in TLB if matched, report TLB
exception if not matched.
With hardware PTW supported, bit Present and Write in pte entry is HW bit.
Bit Present means that the page is valid, and bit Write means that the
page is writable. At the same time HW will set bit Valid with read access,
bit Dirty will be set with write access.
---
v1 ... v2:
1. Add wrapper function loongarch_cmpxchg_phys(), and use
qatomic_cmpxchg() API to update PTW access/dirty bit.
2. Add restart hardware PTW if qatomic_cmpxchg() fails
3. Rename loongarch_page_table_walker() with loongarch_ptw().
4. Add debug parameter in loongarch_ptw(), with debug mode it is to
get physical address only. With normal mode, bit Valid and Dirty
will be update.
---
Bibo Mao (10):
target/loongarch: Use auto method with PTW feature
target/loongarch: Add CSR_PWCH write helper function
target/loongarch: Add present and write bit with pte entry
target/loongarch: Add function sptw_prepare_tlb before adding tlb
entry
target/loongarch: Add common function get_tlb_random_index()
target/loongarch: Add MMUContext parameter in fill_tlb_entry()
target/loongarch: Add debug parameter with
loongarch_page_table_walker()
target/loongarch: Add basic hardware PTW support
target/loongarch: Update matched ptw bit A/D with PTW supported
target/loongarch: Add bit A/D checking in TLB entry with PTW supported
target/loongarch/cpu-csr.h | 4 +
target/loongarch/cpu-mmu.h | 60 ++++++++
target/loongarch/cpu.c | 22 +++
target/loongarch/cpu.h | 2 +
target/loongarch/cpu_helper.c | 114 +++++++++++++--
target/loongarch/tcg/csr_helper.c | 15 ++
target/loongarch/tcg/helper.h | 1 +
.../tcg/insn_trans/trans_privileged.c.inc | 1 +
target/loongarch/tcg/tlb_helper.c | 138 +++++++++++++-----
9 files changed, 310 insertions(+), 47 deletions(-)
base-commit: e013d94c0fd78e88ca78bc90d323626c97076fd3
--
2.39.3
