Hi all,
Thanks Richard for the review. In patch v8:
Richard gave some good improvements, but I don't have time or energy to
do them now. So this patch only fixes the clear and easy problems first.
1. Use the right TCGv type for each variable — for example, make mask_elem
type TCGv_i64.
2. Use tcg_gen_trunc_i64_ptr() to change TCGv types — don't use C-style
casting.
3. Use TCG_COND_TSTNE, not TCG_COND_NE in tcg_gen_brcond_i64() to represent:
if (vext_elem_mask(v0, i) != 0)
History of changes:
patch v7:
- Standardize the subject line of patch 1 and remove the trailing period.
- Split into sub-functions to improve the patch's code readability and
facilitate review.
- Use more faster TCG ops, use tcg_gen_andi_tl() instead of tcg_gen_rem_tl().
- Add a tested-by signature for patch 2, as Eric has already tested it.
https://lore.kernel.org/qemu-devel/cover.1756975571.git.chao....@zevorn.cn/
patch v6:
- If a strided vector memory access instruction has non-zero vstart,
check it through vlse/vsse helpers function.
- Adjust the tcg test Makefile.
https://lore.kernel.org/qemu-devel/cover.1756906528.git.chao....@zevorn.cn/
Patch v5:
- Removed the redundant call to mark_vs_dirty(s) within the
gen_ldst_stride_main_loop() function.
https://lore.kernel.org/qemu-riscv/cover.1755609029.git.chao....@zevorn.cn/
Patch v4:
- Use ctz32() replace to for-loop
https://lore.kernel.org/qemu-devel/cover.1755333616.git.chao....@yeah.net/
Patch v3:
- Fix the get_log2() function:
https://lore.kernel.org/qemu-riscv/cover.1755287531.git.chao....@yeah.net/T/#t
- Add test for vlsseg8e32 instruction.
- Rebase on top of the latest master.
Patch v2:
- Split the TCG node emulation of the complex strided load/store operation into
two separate functions to simplify the implementation:
https://lore.kernel.org/qemu-riscv/20250312155547.289642-1-paolo.sav...@embecosm.com/
Patch v1:
- Paolo submitted the initial version of the patch.
https://lore.kernel.org/qemu-devel/20250211182056.412867-1-paolo.sav...@embecosm.com/
Tanks,
Chao
Chao Liu (2):
target/riscv: Use tcg nodes for strided vector ld/st generation
tests/tcg/riscv64: Add test for vlsseg8e32 instruction
target/riscv/insn_trans/trans_rvv.c.inc | 360 +++++++++++++++++++++-
tests/tcg/riscv64/Makefile.softmmu-target | 7 +-
tests/tcg/riscv64/test-vlsseg8e32.S | 107 +++++++
3 files changed, 456 insertions(+), 18 deletions(-)
create mode 100644 tests/tcg/riscv64/test-vlsseg8e32.S
--
2.51.0
