On 9/7/25 11:51 PM, Max Chou wrote:
The Zvqdotq extension is the vector dot-product extension of RISC-V. Signed-off-by: Max Chou <max.c...@sifive.com> ---
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
target/riscv/cpu.c | 1 + target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/tcg/tcg-cpu.c | 5 +++++ 3 files changed, 7 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d055ddf462..d0909f7beb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -187,6 +187,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg), ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh), ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), + ISA_EXT_DATA_ENTRY(zvqdotq, PRIV_VERSION_1_13_0, ext_zvqdotq), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, debug), diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc index e2d116f0df..5da59c22d6 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -100,6 +100,7 @@ BOOL_FIELD(ext_zvfbfmin) BOOL_FIELD(ext_zvfbfwma) BOOL_FIELD(ext_zvfh) BOOL_FIELD(ext_zvfhmin) +BOOL_FIELD(ext_zvqdotq) BOOL_FIELD(ext_smaia) BOOL_FIELD(ext_ssaia) BOOL_FIELD(ext_smctr) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 78fb279184..7015370ab0 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -767,6 +767,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; }+ if (cpu->cfg.ext_zvqdotq && !cpu->cfg.ext_zve32x) {+ error_setg(errp, "Zvqdotq extension requires V or Zve* extensions"); + return; + } + if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) { error_setg( errp,
