Hi!

On 9/9/25 10:25 AM, LIU Zhiwei wrote:
This patch set introduces support for the RISC-V Smmpt (Supervisor
Domain Access Protection) extension. It only includes two sub-extensions:
SMSDID and SMMPT.

This patch set implements the v0.3.4 version of Smmpt
(https://github.com/riscv/riscv-smmtt/releases/tag/v0.3.4).

As there are newer SMMPT specification versions, this patch set is
not intend for merging.

I'm not sure I understood. Do you mean this patch set isn't supposed to be
merged?


Daniel


The implementation is broken down into a series of logical steps:

Patch 1 adds the fundamental definitions for the Smmpt extension,
including
new CSRs (mmpt, msdcfg), their bit-field layouts, and the corresponding
CPU
configuration flags (ext_smmpt, ext_smsdid).

Patch 2 introduces the core logic for Memory Protection Table (MPT)
lookups.
It includes a new file, riscv_smmpt.c, which implements the multi-level
table walk to determine permissions for a given physical address.

Patch 3 integrates the MPT permission checks into the main MMU and TLB
handling pathways. This ensures that both page table walks and final
data accesses are subject to Smmpt protection rules.

Patch 4 adds support for the new fence instructions defined by the Smmpt
extension, specifically `mfence.spa` and `minval.spa`.

Patch 5 enables smmpt and smsdia extendion.

With this series, QEMU can now model systems that utilize the Smmpt
extension for enhanced memory security.

LIU Zhiwei (5):
   target/riscv: Add basic definitions and CSRs for SMMPT
   target/riscv: Implement core SMMPT lookup logic
   target/riscv: Integrate SMMPT checks into MMU and TLB fill
   target/riscv: Implement SMMPT fence instructions
   target/riscv: Enable SMMPT extension

  target/riscv/cpu.c                            |   4 +
  target/riscv/cpu.h                            |   9 +-
  target/riscv/cpu_bits.h                       |  27 ++
  target/riscv/cpu_cfg_fields.h.inc             |   2 +
  target/riscv/cpu_helper.c                     |  81 +++++-
  target/riscv/csr.c                            |  83 ++++++
  target/riscv/insn32.decode                    |   2 +
  .../riscv/insn_trans/trans_privileged.c.inc   |  30 ++
  target/riscv/meson.build                      |   1 +
  target/riscv/pmp.h                            |   3 +
  target/riscv/riscv_smmpt.c                    | 273 ++++++++++++++++++
  target/riscv/riscv_smmpt.h                    |  38 +++
  12 files changed, 548 insertions(+), 5 deletions(-)
  create mode 100644 target/riscv/riscv_smmpt.c
  create mode 100644 target/riscv/riscv_smmpt.h



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