Loop in more Nuvoton folks. -----Original Message----- From: Peter Maydell <[email protected]> Sent: Friday, September 26, 2025 5:08 PM To: Titus Rwantare <[email protected]> Cc: Yubin Zou <[email protected]>; [email protected]; Paolo Bonzini <[email protected]>; CS20 KFTing <[email protected]>; Hao Wu <[email protected]>; [email protected] Subject: Re: [PATCH 2/7] hw/pci-host: add basic Nuvoton PCIe window support
CAUTION - External Email: Do not click links or open attachments unless you acknowledge the sender and content. On Thu, 25 Sept 2025 at 20:40, Titus Rwantare <[email protected]> wrote: > > On Thu, 25 Sept 2025 at 09:38, Peter Maydell <[email protected]> wrote: > > > > On Tue, 9 Sept 2025 at 23:11, Yubin Zou <[email protected]> wrote: > > > > > > From: Titus Rwantare <[email protected]> > > > > > > Adds the windowing registers without address translation > > > > > > Signed-off-by: Titus Rwantare <[email protected]> > > > --- > > > hw/pci-host/npcm_pcierc.c | 223 > > > +++++++++++++++++++++++++++++++++++++- > > > include/hw/pci-host/npcm_pcierc.h | 77 ++++++++++++- > > > 2 files changed, 297 insertions(+), 3 deletions(-) > > > > > > diff --git a/hw/pci-host/npcm_pcierc.c b/hw/pci-host/npcm_pcierc.c > > > index > > > 3afe92e264f6ce4312e94f05b5e908840008df64..bffdec71acaba6562856b3bd > > > d8aec07c3c153323 100644 > > > --- a/hw/pci-host/npcm_pcierc.c > > > +++ b/hw/pci-host/npcm_pcierc.c > > > @@ -16,6 +16,193 @@ > > > #include "qom/object.h" > > > #include "trace.h" > > > > > > +/* Map enabled windows to a memory subregion */ static void > > > +npcm_pcierc_map_enabled(NPCMPCIERCState *s, NPCMPCIEWindow *w) { > > > + MemoryRegion *system = get_system_memory(); > > > > > + /* TODO: set subregion to target translation address */ > > > + /* add subregion starting at the window source address */ > > > + if (!memory_region_is_mapped(&w->mem)) { > > > + memory_region_init(&w->mem, OBJECT(s), name, size); > > > + memory_region_add_subregion(system, bar, &w->mem); > > > + } > > > > This looks weird. Generally devices should not map themselves into > > the system address space, although some of our older pci-host > > devices do for historical reasons. Should we be modelling this some > > other way? > I can update this. What devices are doing it the new way? I'm not sure exactly what your device is doing here in general, but typically the device exposes sysbus MRs to the SoC and the SoC maps those where they ought to go. Is there documentation on what the hardware behaviour is? thanks -- PMM ________________________________ ________________________________ The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.
