Re: [PATCH v3 05/34] target/riscv: Bugfix make bit 62 read-only 0 for sireg* cfg CSR read

[Alistair Francis]

On Wed, Oct 15, 2025 at 6:36 AM Anton Johansson via
<qemu-devel@nongnu.org> wrote:
>
> According to version 20250508 of the privileged specification, a read of
> cyclecfg or instretcfg through sireg* should make the MINH bit
> read-only 0, currently bit 30 is zeroed.
>
> Signed-off-by: Anton Johansson <a...@rev.ng>

Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>

Alistair

> ---
>  target/riscv/csr.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 657179a983..8be33d8f2c 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1542,7 +1542,7 @@ static int rmw_cd_ctr_cfg(CPURISCVState *env, int 
> cfg_index, target_ulong *val,
>              wr_mask &= ~MCYCLECFG_BIT_MINH;
>              env->mcyclecfg = (new_val & wr_mask) | (env->mcyclecfg & 
> ~wr_mask);
>          } else {
> -            *val = env->mcyclecfg &= ~MHPMEVENTH_BIT_MINH;
> +            *val = env->mcyclecfg &= ~MHPMEVENT_BIT_MINH;
>          }
>          break;
>      case 2:             /* INSTRETCFG */
> @@ -1551,7 +1551,7 @@ static int rmw_cd_ctr_cfg(CPURISCVState *env, int 
> cfg_index, target_ulong *val,
>              env->minstretcfg = (new_val & wr_mask) |
>                                 (env->minstretcfg & ~wr_mask);
>          } else {
> -            *val = env->minstretcfg &= ~MHPMEVENTH_BIT_MINH;
> +            *val = env->minstretcfg &= ~MHPMEVENT_BIT_MINH;
>          }
>          break;
>      default:
> --
> 2.51.0
>
>