On Wed, Oct 15, 2025 at 6:34 AM Anton Johansson via <[email protected]> wrote: > > Hi, > > this is a first patchset moving towards single-binary support for riscv. > Additional patchsets for hw/ and target/ are based on this one so it's > best to make sure the approach taken is ok. Most patches in this set > concern fields in CPUArchState which are either widened (usually to > uint64_t) or fixed to a smaller size which handles all use cases. > > General purpose registers and fields mapped to TCG are dealt with by > widening the type and applying an offset to tcg_global_mem_new() to > correctly handle 32-bit targets on big endian hosts. > > Quick question to correct my understanding. AFAICT riscv64-softmmu is a > superset of riscv32-softmmu which handles 32-, 64, and 128-bit ISAs, so > concerning single-binary do we for the time being only need to support > riscv64-softmmu?
That's correct, the idea is that someone can use riscv64-softmmu for 32, 64 and 128 bit CPUs. So in theory we could remove riscv32-softmmu today and not break anything (obviously it would break a lot due to the name and argument changes required, but you get the point). I don't think many people are using riscv64-softmmu with 32-bit CPUs, so it's possible there are bugs where we accidently expose the wrong thing, but the idea is there and we should work on fixing those. Alistair > > Let me know what you think of the direction taken here and if you would > prefer something else. > > Patches 4, 5, and 10 still in need of review. > > Changes in v2: > - Use BIT() to define misa extension bits in "Use 32 bits for misa > extensions"; > > - Squash "Fix size of mcause" into "Fix size of trivial CPUArchState > fields"; > > - Bump VMSTATE version_id and minimum_version_id for "cpu/pmp/entry", > "cpu/pmp", "cpu/hyper", "cpu/vector", "cpu/rv128", "cpu/debug", > "cpu/envcfg", "cpu/pmu", "cpu/jvt", "cpu/ssp", and "cpu". Migration > from older versions is broken. > > Changes in v3: > - Fix formatting issues during printing; > > - Move assert before extract64() in pmu_read_ctr(); > > - Added patch 5/34 fixing a bug in rmw_cd_ctr_cfg() where bit 30 is > zeroed instead of bit 62 (MHPMEVENTH_* vs MHPMEVENT_*); > > - Added privilege_mode_t typedef for storing PRV_* fields; > > - Added reviewed-bys. > > Anton Johansson (34): > target/riscv: Use 32 bits for misa extensions > target/riscv: Fix size of trivial CPUArchState fields > target/riscv: Fix size of mhartid > target/riscv: Bugfix riscv_pmu_ctr_get_fixed_counters_val() > target/riscv: Bugfix make bit 62 read-only 0 for sireg* cfg CSR read > target/riscv: Combine mhpmevent and mhpmeventh > target/riscv: Combine mcyclecfg and mcyclecfgh > target/riscv: Combine minstretcfg and minstretcfgh > target/riscv: Combine mhpmcounter and mhpmcounterh > target/riscv: Fix size of gpr and gprh > target/riscv: Fix size of vector CSRs > target/riscv: Fix size of pc, load_[val|res] > target/riscv: Fix size of frm and fflags > target/riscv: Fix size of badaddr and bins > target/riscv: Fix size of guest_phys_fault_addr > target/riscv: Fix size of priv_ver and vext_ver > target/riscv: Fix size of retxh > target/riscv: Fix size of ssp > target/riscv: Fix size of excp_uw2 > target/riscv: Fix size of sw_check_code > target/riscv: Fix size of priv > target/riscv: Fix size of gei fields > target/riscv: Fix size of [m|s|vs]iselect fields > target/riscv: Fix arguments to board IMSIC emulation callbacks > target/riscv: Fix size of irq_overflow_left > target/riscv: Indent PMUFixedCtrState correctly > target/riscv: Replace target_ulong in riscv_cpu_get_trap_name() > target/riscv: Replace target_ulong in riscv_ctr_add_entry() > target/riscv: Fix size of trigger data > target/riscv: Fix size of mseccfg > target/riscv: Move debug.h include away from cpu.h > target/riscv: Move CSR declarations to separate csr.h header > target/riscv: Introduce externally facing CSR access functions > target/riscv: Make pmp.h target_ulong agnostic > > target/riscv/cpu.h | 349 +++++++----------- > target/riscv/csr.h | 93 +++++ > target/riscv/debug.h | 2 - > target/riscv/pmp.h | 20 +- > hw/intc/riscv_imsic.c | 34 +- > hw/riscv/riscv_hart.c | 7 +- > linux-user/riscv/signal.c | 5 +- > target/riscv/cpu.c | 10 +- > target/riscv/cpu_helper.c | 42 +-- > target/riscv/csr.c | 290 ++++++++------- > target/riscv/debug.c | 1 + > target/riscv/fpu_helper.c | 6 +- > target/riscv/gdbstub.c | 1 + > target/riscv/kvm/kvm-cpu.c | 1 + > target/riscv/machine.c | 177 +++++---- > target/riscv/op_helper.c | 1 + > target/riscv/pmp.c | 14 +- > target/riscv/pmu.c | 150 ++------ > target/riscv/riscv-qmp-cmds.c | 3 +- > target/riscv/tcg/tcg-cpu.c | 3 +- > target/riscv/th_csr.c | 1 + > target/riscv/translate.c | 53 ++- > target/riscv/vector_helper.c | 22 +- > .../riscv/insn_trans/trans_privileged.c.inc | 2 +- > target/riscv/insn_trans/trans_rvi.c.inc | 16 +- > target/riscv/insn_trans/trans_rvm.c.inc | 16 +- > target/riscv/insn_trans/trans_rvv.c.inc | 24 +- > target/riscv/insn_trans/trans_rvzicfiss.c.inc | 22 +- > 28 files changed, 685 insertions(+), 680 deletions(-) > create mode 100644 target/riscv/csr.h > > -- > 2.51.0 > >
