On 10/3/25 06:26, [email protected] wrote:
From: Alistair Francis <[email protected]>
First RISC-V PR for 10.2 * Fix MSI table size limit * Add riscv64 to FirmwareArchitecture * Sync RISC-V hwprobe with Linux * Implement MonitorDef HMP API * Update OpenSBI to v1.7 * Fix SiFive UART character drop issue and minor refactors * Fix RISC-V timer migration issues * Use riscv_cpu_is_32bit() when handling SBI_DBCN reg * Use riscv_csrr in riscv_csr_read * Align memory allocations to 2M on RISC-V * Do not use translator_ldl in opcode_at * Minor fixes of RISC-V CFI * Modify minimum VLEN rule * Fix vslide1[up|down].vx unexpected result when XLEN=32 and SEW=64 * Fixup IOMMU PDT Nested Walk * Fix endianness swap on compressed instructions * Update status of IOMMU kernel support
Hi! Is there anything in there which is worth picking up for the active stable releases of qemu, which are 10.0.x (lts) and 10.1.x? From the patch descriptions, it seems like quite a few changes in there are worth to be back-ported. For example: - target/riscv: rvv: Fix vslide1[up|down].vx unexpected result when XLEN=32 and SEW=64 - target/riscv: Fix ssamoswap error handling - target/riscv: Fix SSP CSR error handling in VU/VS mode - target/riscv: Fix the mepc when sspopchk triggers the exception - target/riscv: use riscv_csrr in riscv_csr_read - hw/char: sifive_uart: Raise IRQ according to the Tx/Rx watermark thresholds This is just from reading the commit messages, - I haven't looked at the actual changes in the code. Maybe some other changes should be picked up too. I already picked up VLEN fixes, "MSI table size limit" and "do not use translator_ldl in opcode_at" (and I'm still unsure about the latter). Some changes has been Cc'd qemu-stable before, so I picked these up too, eg "Fix endianness swap on compressed instructions" and "Fixup PDT Nested Walk". Some other changes, like the timer array/time delta, does not look like possibilities for the older series due to incompatibility in migration they bring. Thanks, /mjt
