On 10/2/25 20:26, [email protected] wrote:
From: Alistair Francis<[email protected]>
The following changes since commit 29b77c1a2db2d796bc3847852a5c8dc2a1e6e83b:
Merge tag 'rust-ci-pull-request' ofhttps://gitlab.com/marcandre.lureau/qemu
into staging (2025-09-30 09:29:38 -0700)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20251003-3
for you to fetch changes up to ad2a0aa2824b1dac9f61bac33980e866e9a88856:
docs: riscv-iommu: Update status of kernel support (2025-10-03 13:17:04
+1000)
----------------------------------------------------------------
First RISC-V PR for 10.2
* Fix MSI table size limit
* Add riscv64 to FirmwareArchitecture
* Sync RISC-V hwprobe with Linux
* Implement MonitorDef HMP API
* Update OpenSBI to v1.7
* Fix SiFive UART character drop issue and minor refactors
* Fix RISC-V timer migration issues
* Use riscv_cpu_is_32bit() when handling SBI_DBCN reg
* Use riscv_csrr in riscv_csr_read
* Align memory allocations to 2M on RISC-V
* Do not use translator_ldl in opcode_at
* Minor fixes of RISC-V CFI
* Modify minimum VLEN rule
* Fix vslide1[up|down].vx unexpected result when XLEN=32 and SEW=64
* Fixup IOMMU PDT Nested Walk
* Fix endianness swap on compressed instructions
* Update status of IOMMU kernel support
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/10.2 as
appropriate.
r~
