On Wed, Oct 15, 2025 at 6:35 AM Anton Johansson via <[email protected]> wrote: > > 128-bit helpers only make sense for MXL_RV128, TARGET_RISCV64, > and TCGv == TCGv_i64, therefore fix retxh to 64 bits. > > For the sake of being pedandic, update 128-bit instructions to access > retxh via 64 bit TCG ops, even if they only make sense when TCGv == > TCGv_i64. > > Signed-off-by: Anton Johansson <[email protected]> > Reviewed-by: Pierrick Bouvier <[email protected]>
Acked-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/cpu.h | 2 +- > target/riscv/insn_trans/trans_rvi.c.inc | 8 ++++++-- > target/riscv/insn_trans/trans_rvm.c.inc | 16 ++++++++++++---- > 3 files changed, 19 insertions(+), 7 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 6ed912cbd1..d7a41e6db5 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -248,7 +248,7 @@ struct CPUArchState { > uint32_t xl; /* current xlen */ > > /* 128-bit helpers upper part return value */ > - target_ulong retxh; > + uint64_t retxh; > > uint64_t jvt; > > diff --git a/target/riscv/insn_trans/trans_rvi.c.inc > b/target/riscv/insn_trans/trans_rvi.c.inc > index b9c7160468..9c8c04b2dc 100644 > --- a/target/riscv/insn_trans/trans_rvi.c.inc > +++ b/target/riscv/insn_trans/trans_rvi.c.inc > @@ -1012,10 +1012,12 @@ static bool do_csrr_i128(DisasContext *ctx, int rd, > int rc) > TCGv destl = dest_gpr(ctx, rd); > TCGv desth = dest_gprh(ctx, rd); > TCGv_i32 csr = tcg_constant_i32(rc); > + TCGv_i64 wide_desth = tcg_temp_new_i64(); > > translator_io_start(&ctx->base); > gen_helper_csrr_i128(destl, tcg_env, csr); > - tcg_gen_ld_tl(desth, tcg_env, offsetof(CPURISCVState, retxh)); > + tcg_gen_ld_i64(wide_desth, tcg_env, offsetof(CPURISCVState, retxh)); > + tcg_gen_trunc_i64_tl(desth, wide_desth); > gen_set_gpr128(ctx, rd, destl, desth); > return do_csr_post(ctx); > } > @@ -1035,10 +1037,12 @@ static bool do_csrrw_i128(DisasContext *ctx, int rd, > int rc, > TCGv destl = dest_gpr(ctx, rd); > TCGv desth = dest_gprh(ctx, rd); > TCGv_i32 csr = tcg_constant_i32(rc); > + TCGv_i64 wide_desth = tcg_temp_new_i64(); > > translator_io_start(&ctx->base); > gen_helper_csrrw_i128(destl, tcg_env, csr, srcl, srch, maskl, maskh); > - tcg_gen_ld_tl(desth, tcg_env, offsetof(CPURISCVState, retxh)); > + tcg_gen_ld_i64(wide_desth, tcg_env, offsetof(CPURISCVState, retxh)); > + tcg_gen_trunc_i64_tl(desth, wide_desth); > gen_set_gpr128(ctx, rd, destl, desth); > return do_csr_post(ctx); > } > diff --git a/target/riscv/insn_trans/trans_rvm.c.inc > b/target/riscv/insn_trans/trans_rvm.c.inc > index 795f0ccf14..0e2da5bed2 100644 > --- a/target/riscv/insn_trans/trans_rvm.c.inc > +++ b/target/riscv/insn_trans/trans_rvm.c.inc > @@ -169,8 +169,10 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) > static void gen_div_i128(TCGv rdl, TCGv rdh, > TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) > { > + TCGv_i64 wide_rdh = tcg_temp_new_i64(); > gen_helper_divs_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h); > - tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh)); > + tcg_gen_ld_i64(wide_rdh, tcg_env, offsetof(CPURISCVState, retxh)); > + tcg_gen_trunc_i64_tl(rdh, wide_rdh); > } > > static void gen_div(TCGv ret, TCGv source1, TCGv source2) > @@ -212,8 +214,10 @@ static bool trans_div(DisasContext *ctx, arg_div *a) > static void gen_divu_i128(TCGv rdl, TCGv rdh, > TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) > { > + TCGv_i64 wide_rdh = tcg_temp_new_i64(); > gen_helper_divu_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h); > - tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh)); > + tcg_gen_ld_i64(wide_rdh, tcg_env, offsetof(CPURISCVState, retxh)); > + tcg_gen_trunc_i64_tl(rdh, wide_rdh); > } > > static void gen_divu(TCGv ret, TCGv source1, TCGv source2) > @@ -244,8 +248,10 @@ static bool trans_divu(DisasContext *ctx, arg_divu *a) > static void gen_rem_i128(TCGv rdl, TCGv rdh, > TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) > { > + TCGv_i64 wide_rdh = tcg_temp_new_i64(); > gen_helper_rems_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h); > - tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh)); > + tcg_gen_ld_i64(wide_rdh, tcg_env, offsetof(CPURISCVState, retxh)); > + tcg_gen_trunc_i64_tl(rdh, wide_rdh); > } > > static void gen_rem(TCGv ret, TCGv source1, TCGv source2) > @@ -289,8 +295,10 @@ static bool trans_rem(DisasContext *ctx, arg_rem *a) > static void gen_remu_i128(TCGv rdl, TCGv rdh, > TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) > { > + TCGv_i64 wide_rdh = tcg_temp_new_i64(); > gen_helper_remu_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h); > - tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh)); > + tcg_gen_ld_i64(wide_rdh, tcg_env, offsetof(CPURISCVState, retxh)); > + tcg_gen_trunc_i64_tl(rdh, wide_rdh); > } > > static void gen_remu(TCGv ret, TCGv source1, TCGv source2) > -- > 2.51.0 > >
