On Wed, Oct 1, 2025 at 7:49 PM Djordje Todorovic <[email protected]> wrote: > > Add MIPS P8700 prefetch instruction defined by Xmipscbop. > > Signed-off-by: Chao-ying Fu <[email protected]> > Signed-off-by: Djordje Todorovic <[email protected]> > Reviewed-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/cpu.c | 3 +++ > target/riscv/cpu_cfg.h | 2 +- > target/riscv/cpu_cfg_fields.h.inc | 1 + > target/riscv/insn_trans/trans_xmips.c.inc | 15 +++++++++++++++ > target/riscv/xmips.decode | 1 + > 5 files changed, 21 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 77fbf67776..87f9eb7ac4 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -247,6 +247,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(svrsw60t59b, PRIV_VERSION_1_13_0, ext_svrsw60t59b), > ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte), > ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc), > + ISA_EXT_DATA_ENTRY(xmipscbop, PRIV_VERSION_1_12_0, ext_xmipscbop), > ISA_EXT_DATA_ENTRY(xmipscmov, PRIV_VERSION_1_12_0, ext_xmipscmov), > ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), > ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), > @@ -1380,6 +1381,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = { > MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false), > MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false), > MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false), > + MULTI_EXT_CFG_BOOL("xmipscbop", ext_xmipscbop, false), > MULTI_EXT_CFG_BOOL("xmipscmov", ext_xmipscmov, false), > > { }, > @@ -3295,6 +3297,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > .cfg.pmp = true, > .cfg.ext_zba = true, > .cfg.ext_zbb = true, > + .cfg.ext_xmipscbop = true, > .cfg.ext_xmipscmov = true, > .cfg.marchid = 0x8000000000000201, > .cfg.mvendorid = MIPS_VENDOR_ID, > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index 2db471ad17..e4d5039c49 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -38,7 +38,7 @@ static inline bool always_true_p(const RISCVCPUConfig *cfg > __attribute__((__unus > > static inline bool has_xmips_p(const RISCVCPUConfig *cfg) > { > - return cfg->ext_xmipscmov; > + return cfg->ext_xmipscbop || cfg->ext_xmipscmov; > } > > static inline bool has_xthead_p(const RISCVCPUConfig *cfg) > diff --git a/target/riscv/cpu_cfg_fields.h.inc > b/target/riscv/cpu_cfg_fields.h.inc > index a290303ee7..dd3ee7ba2b 100644 > --- a/target/riscv/cpu_cfg_fields.h.inc > +++ b/target/riscv/cpu_cfg_fields.h.inc > @@ -147,6 +147,7 @@ BOOL_FIELD(ext_xtheadmemidx) > BOOL_FIELD(ext_xtheadmempair) > BOOL_FIELD(ext_xtheadsync) > BOOL_FIELD(ext_XVentanaCondOps) > +BOOL_FIELD(ext_xmipscbop) > BOOL_FIELD(ext_xmipscmov) > > BOOL_FIELD(mmu) > diff --git a/target/riscv/insn_trans/trans_xmips.c.inc > b/target/riscv/insn_trans/trans_xmips.c.inc > index 3202fd9cc0..bfe9046153 100644 > --- a/target/riscv/insn_trans/trans_xmips.c.inc > +++ b/target/riscv/insn_trans/trans_xmips.c.inc > @@ -9,6 +9,12 @@ > * (https://mips.com/products/hardware/p8700/) > */ > > +#define REQUIRE_XMIPSCBOP(ctx) do { \ > + if (!ctx->cfg_ptr->ext_xmipscbop) { \ > + return false; \ > + } \ > +} while (0) > + > #define REQUIRE_XMIPSCMOV(ctx) do { \ > if (!ctx->cfg_ptr->ext_xmipscmov) { \ > return false; \ > @@ -31,3 +37,12 @@ static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a) > > return true; > } > + > +/* Move data from memory into cache. */ > +static bool trans_pref(DisasContext *ctx, arg_pref *a) > +{ > + REQUIRE_XMIPSCBOP(ctx); > + > + /* Nop */ > + return true; > +} > diff --git a/target/riscv/xmips.decode b/target/riscv/xmips.decode > index fadcb78470..4215813b32 100644 > --- a/target/riscv/xmips.decode > +++ b/target/riscv/xmips.decode > @@ -9,3 +9,4 @@ > # (https://mips.com/products/hardware/p8700/) > > ccmov rs3:5 11 rs2:5 rs1:5 011 rd:5 0001011 > +pref 000 imm_9:9 rs1:5 000 imm_hint:5 0001011 > -- > 2.34.1
