From: Max Chou <[email protected]> The Zve32x extension will be applied by the V and Zve* extensions. Therefore we can replace the original V checking with Zve32x checking for both the V and Zve* extensions.
Signed-off-by: Max Chou <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-ID: <[email protected]> Signed-off-by: Alistair Francis <[email protected]> (cherry picked from commit ae4a37f57818e47e212272821a5a86ad54620eb8) (Mjt: drop the MonitorDef change due to missing v10.1.0-850-ge06d209aa6 "target/riscv: implement MonitorDef HMP API") Signed-off-by: Michael Tokarev <[email protected]> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 09ded6829a..2ff56bd017 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -945,7 +945,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) } } } - if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) { + if (riscv_cpu_cfg(env)->ext_zve32x && (flags & CPU_DUMP_VPU)) { static const int dump_rvv_csrs[] = { CSR_VSTART, CSR_VXSAT, diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 66d572af1f..76e2f7e1d5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1990,7 +1990,8 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, if (riscv_has_ext(env, RVF)) { mask |= MSTATUS_FS; } - if (riscv_has_ext(env, RVV)) { + + if (riscv_cpu_cfg(env)->ext_zve32x) { mask |= MSTATUS_VS; } diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 889e2b6570..0697d813b7 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -130,7 +130,8 @@ static bool vector_needed(void *opaque) RISCVCPU *cpu = opaque; CPURISCVState *env = &cpu->env; - return riscv_has_ext(env, RVV); + return kvm_enabled() ? riscv_has_ext(env, RVV) : + riscv_cpu_cfg(env)->ext_zve32x; } static const VMStateDescription vmstate_vector = { diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 5aef9eef36..2b21580ef7 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -515,7 +515,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } - if (riscv_has_ext(env, RVV)) { + if (cpu->cfg.ext_zve32x) { riscv_cpu_validate_v(env, &cpu->cfg, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); -- 2.47.3
