On Tue, Oct 14, 2025 at 1:00 AM Zejun Zhao <[email protected]> wrote:
>
> Correct mmu-type property of sifive_u harts from Sv48 to Sv39 in 64-bit
> mode since it's the only supported SATP mode.
>
> Signed-off-by: Zejun Zhao <[email protected]>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> hw/riscv/sifive_u.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index d69f942cfb..3e1ed209ca 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -176,7 +176,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry
> *memmap,
> if (is_32_bit) {
> qemu_fdt_setprop_string(fdt, nodename, "mmu-type",
> "riscv,sv32");
> } else {
> - qemu_fdt_setprop_string(fdt, nodename, "mmu-type",
> "riscv,sv48");
> + qemu_fdt_setprop_string(fdt, nodename, "mmu-type",
> "riscv,sv39");
> }
> riscv_isa_write_fdt(&s->soc.u_cpus.harts[cpu - 1], fdt,
> nodename);
> } else {
> --
> 2.43.0
>
>
