We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code.
This change places hooks for ARM (and Aarch64) targets. We decided to treat the (V)IRQ, (VI/VF)NMI, (V)FIQ and VSERR exceptions as interrupts since they are, presumably, async in nature. Reviewed-by: Richard Henderson <[email protected]> Signed-off-by: Julian Ganz <[email protected]> --- target/arm/helper.c | 24 ++++++++++++++++++++++++ target/arm/internals.h | 1 + target/arm/tcg/m_helper.c | 5 +++++ 3 files changed, 30 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 167f2909b3..c30d77bee9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -34,6 +34,7 @@ #endif #include "cpregs.h" #include "target/arm/gtimer.h" +#include "qemu/plugin.h" #define HELPER_H "tcg/helper.h" #include "exec/helper-proto.h.inc" @@ -8715,6 +8716,24 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, } } +void arm_do_plugin_vcpu_discon_cb(CPUState *cs, uint64_t from) +{ + switch (cs->exception_index) { + case EXCP_IRQ: + case EXCP_VIRQ: + case EXCP_NMI: + case EXCP_VINMI: + case EXCP_FIQ: + case EXCP_VFIQ: + case EXCP_VFNMI: + case EXCP_VSERR: + qemu_plugin_vcpu_interrupt_cb(cs, from); + break; + default: + qemu_plugin_vcpu_exception_cb(cs, from); + } +} + static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) { /* @@ -9405,6 +9424,7 @@ void arm_cpu_do_interrupt(CPUState *cs) ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; unsigned int new_el = env->exception.target_el; + uint64_t last_pc = cs->cc->get_pc(cs); assert(!arm_feature(env, ARM_FEATURE_M)); @@ -9421,6 +9441,7 @@ void arm_cpu_do_interrupt(CPUState *cs) if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) { arm_handle_psci_call(cpu); qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); + qemu_plugin_vcpu_hostcall_cb(cs, last_pc); return; } @@ -9432,6 +9453,7 @@ void arm_cpu_do_interrupt(CPUState *cs) #ifdef CONFIG_TCG if (cs->exception_index == EXCP_SEMIHOST) { tcg_handle_semihosting(cs); + qemu_plugin_vcpu_hostcall_cb(cs, last_pc); return; } #endif @@ -9457,6 +9479,8 @@ void arm_cpu_do_interrupt(CPUState *cs) if (!kvm_enabled()) { cpu_set_interrupt(cs, CPU_INTERRUPT_EXITTB); } + + arm_do_plugin_vcpu_discon_cb(cs, last_pc); } #endif /* !CONFIG_USER_ONLY */ diff --git a/target/arm/internals.h b/target/arm/internals.h index f539bbe58e..6be044b29d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -375,6 +375,7 @@ static inline int r14_bank_number(int mode) void arm_cpu_register(const ARMCPUInfo *info); +void arm_do_plugin_vcpu_discon_cb(CPUState *cs, uint64_t from); void register_cp_regs_for_features(ARMCPU *cpu); void init_cpreg_list(ARMCPU *cpu); diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index d856e3bc8e..3fb24c7790 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -23,6 +23,7 @@ #if !defined(CONFIG_USER_ONLY) #include "hw/intc/armv7m_nvic.h" #endif +#include "qemu/plugin.h" static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, uint32_t reg, uint32_t val) @@ -2194,6 +2195,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) CPUARMState *env = &cpu->env; uint32_t lr; bool ignore_stackfaults; + uint64_t last_pc = env->regs[15]; arm_log_exception(cs); @@ -2361,6 +2363,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) g_assert_not_reached(); #endif env->regs[15] += env->thumb ? 2 : 4; + qemu_plugin_vcpu_hostcall_cb(cs, last_pc); return; case EXCP_BKPT: armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false); @@ -2427,6 +2430,8 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) ignore_stackfaults = v7m_push_stack(cpu); v7m_exception_taken(cpu, lr, false, ignore_stackfaults); + + arm_do_plugin_vcpu_discon_cb(cs, last_pc); } uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) -- 2.49.1
