From: Anton Johansson <[email protected]> According to version 20250508 of the privileged specification, a read of cyclecfg or instretcfg through sireg* should make the MINH bit read-only 0, currently bit 30 is zeroed.
Signed-off-by: Anton Johansson <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Reviewed-by: Pierrick Bouvier <[email protected]> Message-ID: <[email protected]> Signed-off-by: Alistair Francis <[email protected]> --- target/riscv/csr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5c91658c3d..b0917f27bb 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1544,7 +1544,7 @@ static int rmw_cd_ctr_cfg(CPURISCVState *env, int cfg_index, target_ulong *val, wr_mask &= ~MCYCLECFG_BIT_MINH; env->mcyclecfg = (new_val & wr_mask) | (env->mcyclecfg & ~wr_mask); } else { - *val = env->mcyclecfg &= ~MHPMEVENTH_BIT_MINH; + *val = env->mcyclecfg &= ~MHPMEVENT_BIT_MINH; } break; case 2: /* INSTRETCFG */ @@ -1553,7 +1553,7 @@ static int rmw_cd_ctr_cfg(CPURISCVState *env, int cfg_index, target_ulong *val, env->minstretcfg = (new_val & wr_mask) | (env->minstretcfg & ~wr_mask); } else { - *val = env->minstretcfg &= ~MHPMEVENTH_BIT_MINH; + *val = env->minstretcfg &= ~MHPMEVENT_BIT_MINH; } break; default: -- 2.51.1
