Widen to 64 bits in size to hold all relevant values. Note: src and dst arguments change from signed to unsigned but no functional change is incurred.
Signed-off-by: Anton Johansson <[email protected]> Reviewed-by: Pierrick Bouvier <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Acked-by: Alistair Francis <[email protected]> --- target/riscv/cpu.h | 5 +++-- target/riscv/cpu_helper.c | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c2be30795a..ee4444f22d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -662,8 +662,9 @@ RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); void riscv_cpu_set_mode(CPURISCVState *env, privilege_mode_t newpriv, bool virt_en); -void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long dst, - enum CTRType type, privilege_mode_t prev_priv, bool prev_virt); +void riscv_ctr_add_entry(CPURISCVState *env, uint64_t src, uint64_t dst, + enum CTRType type, privilege_mode_t prev_priv, + bool prev_virt); void riscv_ctr_clear(CPURISCVState *env); void riscv_translate_init(void); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b102f15ac6..20ff05a4b2 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -926,8 +926,9 @@ static bool riscv_ctr_check_xte(CPURISCVState *env, * entry = isel - CTR_ENTRIES_FIRST; * idx = (sctrstatus.WRPTR - entry - 1) & (depth - 1); */ -void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long dst, - enum CTRType type, privilege_mode_t src_priv, bool src_virt) +void riscv_ctr_add_entry(CPURISCVState *env, uint64_t src, uint64_t dst, + enum CTRType type, privilege_mode_t src_priv, + bool src_virt) { bool tgt_virt = env->virt_enabled; uint64_t src_mask = riscv_ctr_priv_to_mask(src_priv, src_virt); -- 2.51.0
