On Mon, 3 Nov 2025, BALATON Zoltan wrote:
On Sun, 2 Nov 2025, Chad Jablonski wrote:
Writing to any of the HOST_DATA0-7 registers pushes the written data
into a buffer. A final write to HOST_DATA_LAST writes data to the
buffer and triggers the pending blit operation.
The buffer for now is a static 4MiB and overflows are checked. This
seems like a large enough value given what I've seen in testing. Future
work could dynamically size the buffer based on the destination dimensions
if
needed.
I wonder where the real chip stores this information?
I don't think there's a separate buffer for this on real card and the
command FIFO is not long enough to store it so it should probably use
vram. But how does it know which part of that can be used? Maybe you could
write some pattern into HOST_DATAx registers (like 0xaaaaaaaa, 0x55555555
but longer than the FIFO to make sure it's not staying there) and then
before writing HOST_DATA_LAST look for that pattern in vram to see if it
appears anywhere. Maybe some register points there or the card has some
memory management I don't know about? (I don't know much about GPUs so
it's quite possible I have no idea how it should work.) If the pattern is
not found I don't have any better idea to find out how this should work.
(We could keep the separate buffer in emulation for now but I'm curious
how the real chip does it and if we can emulate that.)
Regards,
BALATON Zoltan
