>> >> I wonder where the real chip stores this information? > > I don't think there's a separate buffer for this on real card and the > command FIFO is not long enough to store it so it should probably use > vram. But how does it know which part of that can be used? Maybe you could > write some pattern into HOST_DATAx registers (like 0xaaaaaaaa, 0x55555555 > but longer than the FIFO to make sure it's not staying there) and then > before writing HOST_DATA_LAST look for that pattern in vram to see if it > appears anywhere. Maybe some register points there or the card has some > memory management I don't know about? (I don't know much about GPUs so > it's quite possible I have no idea how it should work.) If the pattern is > not found I don't have any better idea to find out how this should work. > (We could keep the separate buffer in emulation for now but I'm curious > how the real chip does it and if we can emulate that.) > > Regards, > BALATON Zoltan
Hi BALATON, You're absolutely right. After spending some time setting up a nicer test environment I'm able to confirm this behavior on the Rage 128 Pro Ultra TF: write HOST_DATA0 write HOST_DATA1 write HOST_DATA2 write HOST_DATA3 -> Data appears in the framebuffer at the destination write HOST_DATA4 write HOST_DATA5 write HOST_DATA6 write HOST_DATA7 -> Data appears in the framebuffer at the destination The card does not wait for HOST_DATA_LAST to flush to the destination. So it would appear that there is no buffer at all or even a special area in VRAM. It's looking like there is a 128-bit accumulator which makes total sense given the architecture of the card. I'd like to do some additional testing but you were right to question this. I'll address it in patch v3.
