Add bfloat16 and ieee_half fields to the RISC-V FPU register unions in the GDB target description XML files. This allows GDB to access FPU registers as BFloat16 or IEEE half-precision floating-point values in addition to the existing single and double precision formats.
For 64-bit FPU (riscv-64bit-fpu.xml): - Add bfloat16 field to riscv_double union - Add half (ieee_half) field to riscv_double union For 32-bit FPU (riscv-32bit-fpu.xml): - Create new riscv_single union with bfloat16, half, and float fields - Update all 32 FPU registers to use riscv_single type instead of ieee_single This enables GDB users to inspect and modify FPU registers using different floating-point formats: (gdb) print \.bfloat16 (gdb) print \.half (gdb) print \.float (gdb) print \.double This change corresponds to the GDB-side support for these formats: https://sourceware.org/pipermail/gdb-patches/2025-November/222353.html Signed-off-by: Jerry Zhang Jian <[email protected]> --- gdb-xml/riscv-32bit-fpu.xml | 70 ++++++++++++++++++++----------------- gdb-xml/riscv-64bit-fpu.xml | 2 ++ 2 files changed, 40 insertions(+), 32 deletions(-) diff --git a/gdb-xml/riscv-32bit-fpu.xml b/gdb-xml/riscv-32bit-fpu.xml index 24aa087031..f0439c626e 100644 --- a/gdb-xml/riscv-32bit-fpu.xml +++ b/gdb-xml/riscv-32bit-fpu.xml @@ -7,36 +7,42 @@ <!DOCTYPE feature SYSTEM "gdb-target.dtd"> <feature name="org.gnu.gdb.riscv.fpu"> - <reg name="ft0" bitsize="32" type="ieee_single"/> - <reg name="ft1" bitsize="32" type="ieee_single"/> - <reg name="ft2" bitsize="32" type="ieee_single"/> - <reg name="ft3" bitsize="32" type="ieee_single"/> - <reg name="ft4" bitsize="32" type="ieee_single"/> - <reg name="ft5" bitsize="32" type="ieee_single"/> - <reg name="ft6" bitsize="32" type="ieee_single"/> - <reg name="ft7" bitsize="32" type="ieee_single"/> - <reg name="fs0" bitsize="32" type="ieee_single"/> - <reg name="fs1" bitsize="32" type="ieee_single"/> - <reg name="fa0" bitsize="32" type="ieee_single"/> - <reg name="fa1" bitsize="32" type="ieee_single"/> - <reg name="fa2" bitsize="32" type="ieee_single"/> - <reg name="fa3" bitsize="32" type="ieee_single"/> - <reg name="fa4" bitsize="32" type="ieee_single"/> - <reg name="fa5" bitsize="32" type="ieee_single"/> - <reg name="fa6" bitsize="32" type="ieee_single"/> - <reg name="fa7" bitsize="32" type="ieee_single"/> - <reg name="fs2" bitsize="32" type="ieee_single"/> - <reg name="fs3" bitsize="32" type="ieee_single"/> - <reg name="fs4" bitsize="32" type="ieee_single"/> - <reg name="fs5" bitsize="32" type="ieee_single"/> - <reg name="fs6" bitsize="32" type="ieee_single"/> - <reg name="fs7" bitsize="32" type="ieee_single"/> - <reg name="fs8" bitsize="32" type="ieee_single"/> - <reg name="fs9" bitsize="32" type="ieee_single"/> - <reg name="fs10" bitsize="32" type="ieee_single"/> - <reg name="fs11" bitsize="32" type="ieee_single"/> - <reg name="ft8" bitsize="32" type="ieee_single"/> - <reg name="ft9" bitsize="32" type="ieee_single"/> - <reg name="ft10" bitsize="32" type="ieee_single"/> - <reg name="ft11" bitsize="32" type="ieee_single"/> + <union id="riscv_single"> + <field name="bfloat16" type="bfloat16"/> + <field name="half" type="ieee_half"/> + <field name="float" type="ieee_single"/> + </union> + + <reg name="ft0" bitsize="32" type="riscv_single"/> + <reg name="ft1" bitsize="32" type="riscv_single"/> + <reg name="ft2" bitsize="32" type="riscv_single"/> + <reg name="ft3" bitsize="32" type="riscv_single"/> + <reg name="ft4" bitsize="32" type="riscv_single"/> + <reg name="ft5" bitsize="32" type="riscv_single"/> + <reg name="ft6" bitsize="32" type="riscv_single"/> + <reg name="ft7" bitsize="32" type="riscv_single"/> + <reg name="fs0" bitsize="32" type="riscv_single"/> + <reg name="fs1" bitsize="32" type="riscv_single"/> + <reg name="fa0" bitsize="32" type="riscv_single"/> + <reg name="fa1" bitsize="32" type="riscv_single"/> + <reg name="fa2" bitsize="32" type="riscv_single"/> + <reg name="fa3" bitsize="32" type="riscv_single"/> + <reg name="fa4" bitsize="32" type="riscv_single"/> + <reg name="fa5" bitsize="32" type="riscv_single"/> + <reg name="fa6" bitsize="32" type="riscv_single"/> + <reg name="fa7" bitsize="32" type="riscv_single"/> + <reg name="fs2" bitsize="32" type="riscv_single"/> + <reg name="fs3" bitsize="32" type="riscv_single"/> + <reg name="fs4" bitsize="32" type="riscv_single"/> + <reg name="fs5" bitsize="32" type="riscv_single"/> + <reg name="fs6" bitsize="32" type="riscv_single"/> + <reg name="fs7" bitsize="32" type="riscv_single"/> + <reg name="fs8" bitsize="32" type="riscv_single"/> + <reg name="fs9" bitsize="32" type="riscv_single"/> + <reg name="fs10" bitsize="32" type="riscv_single"/> + <reg name="fs11" bitsize="32" type="riscv_single"/> + <reg name="ft8" bitsize="32" type="riscv_single"/> + <reg name="ft9" bitsize="32" type="riscv_single"/> + <reg name="ft10" bitsize="32" type="riscv_single"/> + <reg name="ft11" bitsize="32" type="riscv_single"/> </feature> diff --git a/gdb-xml/riscv-64bit-fpu.xml b/gdb-xml/riscv-64bit-fpu.xml index d0f17f9984..7d6a44e145 100644 --- a/gdb-xml/riscv-64bit-fpu.xml +++ b/gdb-xml/riscv-64bit-fpu.xml @@ -9,6 +9,8 @@ <feature name="org.gnu.gdb.riscv.fpu"> <union id="riscv_double"> + <field name="bfloat16" type="bfloat16"/> + <field name="half" type="ieee_half"/> <field name="float" type="ieee_single"/> <field name="double" type="ieee_double"/> </union> -- 2.51.0
