Hi,

In this new version we addressed the comments from Chao Liu in patches 2
and 4.

We're also owning up the fact that the board is being contributed in an
incomplete status, given that we're missing 'sdext'.In theory we
shouldn't try to upstream it until we have 'sdext' implemented but this
board seems to be used by a lot of folks for for firmware development
and whatnot. Thus, I changed the board description in patch 3 to add an
'EXPERIMENTAL' tag.

This is how the board is presented with -M help:

$ ./build/qemu-system-riscv64 -M help Supported machines are:
amd-microblaze-v-generic AMD Microblaze-V generic platform
microchip-icicle-kit Microchip PolarFire SoC Icicle Kit none
empty machine rvsp-ref             RISC-V Server SoC Reference board
(EXPERIMENTAL) (...)

Patch 5 adds documentation for the board. Again, making it clear that
this is an experimental board that will be subject to changes before
being 100% compliant with the spec.

Patches based on current master.

Changes in v4:
- patch 2:
  - changed rvsp-ref CPU base type to BARE
  - added a comment mentioning the lack of 'sdext'
- patch 3:
  - changed the board description to add 'experimental'
- patch 4:
  - fixed RVSP_IOMMU_SYS memmap addr: 0102000 -> 0x102000
- patch 5 (new):
  - add board documentation
- v3 link: 
https://lore.kernel.org/qemu-riscv/[email protected]/
 


Daniel Henrique Barboza (3):
  target/riscv/cpu.c: remove 'bare' condition for .profile
  hw/riscv/server_platform_ref.c: add riscv-iommu-sys
  docs: add rvsp-ref.rst

Fei Wu (2):
  target/riscv: Add server platform reference cpu
  hw/riscv: experimental server platform reference machine

 configs/devices/riscv64-softmmu/default.mak |    1 +
 docs/system/riscv/rvsp-ref.rst              |   28 +
 docs/system/target-riscv.rst                |    1 +
 hw/riscv/Kconfig                            |   15 +
 hw/riscv/meson.build                        |    1 +
 hw/riscv/server_platform_ref.c              | 1346 +++++++++++++++++++
 target/riscv/cpu-qom.h                      |    1 +
 target/riscv/cpu.c                          |   15 +-
 8 files changed, 1407 insertions(+), 1 deletion(-)
 create mode 100644 docs/system/riscv/rvsp-ref.rst
 create mode 100644 hw/riscv/server_platform_ref.c

-- 
2.51.1


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