On 11/11/25 8:05 PM, Andrew Jones wrote:
On Tue, Nov 11, 2025 at 03:29:41PM -0300, Daniel Henrique Barboza wrote:
From: Fei Wu <[email protected]>
The harts requirements of RISC-V server platform [1] require RVA23 ISA
profile support, plus Sv48, Svadu, H, Sscofmpf etc.
This patch provides a CPU type (rvsp-ref) to go along with the rvsp-ref
board.
[1]
https://github.com/riscv-non-isa/riscv-server-platform/blob/main/server_platform_requirements.adoc
Signed-off-by: Fei Wu <[email protected]>
Signed-off-by: Daniel Henrique Barboza <[email protected]>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 14 ++++++++++++++
2 files changed, 15 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 75f4e43408..07e96a14ba 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -42,6 +42,7 @@
#define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64")
#define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64")
#define TYPE_RISCV_CPU_RVA23S64 RISCV_CPU_TYPE_NAME("rva23s64")
+#define TYPE_RISCV_CPU_RVSP_REF RISCV_CPU_TYPE_NAME("rvsp-ref")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
#define TYPE_RISCV_CPU_SIFIVE_E RISCV_CPU_TYPE_NAME("sifive-e")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 975f7953e1..3ddb249970 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3305,6 +3305,20 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.max_satp_mode = VM_1_10_SV48,
),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RVSP_REF, TYPE_RISCV_BARE_CPU,
+ .misa_mxl_max = MXL_RV64,
+ .profile = &RVA23S64,
+
+ /*
+ * ISA extensions
+ * NOTE: we're missing 'sdext'.
+ */
+ .cfg.ext_zkr = true,
+ .cfg.ext_svadu = true,
Svadu is no longer required.
+
+ .cfg.max_satp_mode = VM_1_10_SV57,
Shouldn't this be SV48 and then allow instantiations to use
rvsp-ref,sv57=on.
Makes sense.
We also need Ssccfg and Sdtrig.
Sdtrig is enabled by default, and somehow I forgot to add ssccfg. I'll add it.
Thanks,
Daniel
+ ),
+
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU,
.cfg.max_satp_mode = VM_1_10_SV57,
--
2.51.1
Thanks,
drew
