On 13/11/2025 06:41, Mark Cave-Ayland wrote:
+struct Neorv32UARTState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + qemu_irq irq; + MemoryRegion mmio; + CharFrontend chr; + uint8_t rx_fifo[NEORV32_UART_RX_FIFO_SIZE]; + uint8_t rx_fifo_len;Rather than re-invent your own FIFO, can you make use of the existing Fifo8? It has a much richer API, and as long as you don't use the deprecated _bufptr() APIs, it will aggressively defend against underflow/overflow.
This looks like it is possible even with the configurable UART size, since that is exactly how the FIFO is implemented for the SPI device introduced in the following patch.
ATB, Mark.
