From: Anton Blanchard <[email protected]> Handle the overlap of source registers with different EEWs for vector reduction instructions.
Signed-off-by: Anton Blanchard <[email protected]> Reviewed-by: Nutty Liu <[email protected]> Signed-off-by: Max Chou <[email protected]> --- target/riscv/insn_trans/trans_rvv.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 422e1a21185..2d9cf27ef76 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3076,6 +3076,7 @@ static bool reduction_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && vext_check_isa_ill(s) && + vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew, a->vm) && vext_check_reduction(s, a->rs2); } @@ -3092,7 +3093,8 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check) static bool reduction_widen_check(DisasContext *s, arg_rmrr *a) { return reduction_check(s, a) && (s->sew < MO_64) && - ((s->sew + 1) <= (s->cfg_ptr->elen >> 4)); + ((s->sew + 1) <= (s->cfg_ptr->elen >> 4)) && + vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew + 1, a->vm); } GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check) -- 2.43.0
