On 11/17/25 02:40, Gabriel Brookman wrote:
These are the bitmasks used to control the FEAT_MTE_STORE_ONLY feature.
They are now named and setting these fields of SCTLR is ignored if MTE
is disabled, as per convention.
Signed-off-by: Gabriel Brookman <[email protected]>
---
target/arm/cpu.h | 2 ++
target/arm/helper.c | 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 39f2b2e54d..6fe85b5e3a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1424,6 +1424,8 @@ void pmu_init(ARMCPU *cpu);
#define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */
#define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */
#define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */
+#define SCTLR_TCSO0 (1ULL << 58) /* FEAT_MTE_STORE_ONLY */
+#define SCTLR_TCSO (1ULL << 59) /* FEAT_MTE_STORE_ONLY */
#define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */
Indentation is off.
@@ -3364,10 +3364,10 @@ static void sctlr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) {
if (ri->opc1 == 6) { /* SCTLR_EL3 */
- value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA);
+ value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA | SCTLR_TCSO);
} else {
value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF |
- SCTLR_ATA0 | SCTLR_ATA);
+ SCTLR_ATA0 | SCTLR_ATA | SCTLR_TCSO | SCTLR_TCSO0);
}
}
You should be testing for FEAT_MTE_STORE_ONLY, not just plain MTE (since
renamed MTE2).
Add the appropriate function to cpu-features.h.
r~
