Hardware testing on the Rage 128 confirms that (SRC/DST)_OFFSET, and (SRC/DST)_PITCH are latched when (SRC/DST)_PITCH_OFFSET_CNTL bits in DP_GUI_MASTER_CNTL are set to "default".
The earlier approach looked at the state of the (SRC/DST)_PITCH_OFFSET_CNTL bits when offset and pitch registers were used. This meant that when (SRC/DST)_PITCH_OFFSET_CNTL was reset to "leave alone" the old values stored in the registers would return. This is not how the real hardware works. Signed-off-by: Chad Jablonski <[email protected]> --- hw/display/ati.c | 8 ++++++++ hw/display/ati_2d.c | 13 ++++--------- hw/display/ati_regs.h | 10 ++++++++++ 3 files changed, 22 insertions(+), 9 deletions(-) diff --git a/hw/display/ati.c b/hw/display/ati.c index a2c0302e42..d0fa51f773 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -888,6 +888,14 @@ static void ati_mm_write(void *opaque, hwaddr addr, (data & 0x4000) << 16; s->regs.dp_mix = (data & GMC_ROP3_MASK) | (data & 0x7000000) >> 16; + if ((data & GMC_SRC_PITCH_OFFSET_CNTL_MASK) == GMC_SRC_PITCH_OFFSET_DEFAULT) { + s->regs.src_offset = s->regs.default_offset; + s->regs.src_pitch = s->regs.default_pitch; + } + if ((data & GMC_DST_PITCH_OFFSET_CNTL_MASK) == GMC_DST_PITCH_OFFSET_DEFAULT) { + s->regs.dst_offset = s->regs.default_offset; + s->regs.dst_pitch = s->regs.default_pitch; + } if ((data & GMC_SRC_CLIPPING_MASK) == GMC_SRC_CLIP_DEFAULT) { s->regs.src_sc_right = s->regs.default_sc_right; s->regs.src_sc_bottom = s->regs.default_sc_bottom; diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index 309bb5ccb6..a8c4c534b9 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -43,8 +43,6 @@ static int ati_bpp_from_datatype(ATIVGAState *s) } } -#define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL) - void ati_2d_blt(ATIVGAState *s) { /* FIXME it is probably more complex than this and may need to be */ @@ -63,13 +61,12 @@ void ati_2d_blt(ATIVGAState *s) qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n"); return; } - int dst_stride = DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_pitch; + int dst_stride = s->regs.dst_pitch; if (!dst_stride) { qemu_log_mask(LOG_GUEST_ERROR, "Zero dest pitch\n"); return; } - uint8_t *dst_bits = s->vga.vram_ptr + (DEFAULT_CNTL ? - s->regs.dst_offset : s->regs.default_offset); + uint8_t *dst_bits = s->vga.vram_ptr + s->regs.dst_offset; if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { dst_bits += s->regs.crtc_offset & 0x07ffffff; @@ -97,14 +94,12 @@ void ati_2d_blt(ATIVGAState *s) s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_width); unsigned src_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_height); - int src_stride = DEFAULT_CNTL ? - s->regs.src_pitch : s->regs.default_pitch; + int src_stride = s->regs.src_pitch; if (!src_stride) { qemu_log_mask(LOG_GUEST_ERROR, "Zero source pitch\n"); return; } - uint8_t *src_bits = s->vga.vram_ptr + (DEFAULT_CNTL ? - s->regs.src_offset : s->regs.default_offset); + uint8_t *src_bits = s->vga.vram_ptr + s->regs.src_offset; if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { src_bits += s->regs.crtc_offset & 0x07ffffff; diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h index 2b56b9fb66..02025eef36 100644 --- a/hw/display/ati_regs.h +++ b/hw/display/ati_regs.h @@ -402,6 +402,16 @@ #define GMC_WRITE_MASK_SET 0x40000000 #define GMC_DP_CONVERSION_TEMP_6500 0x00000000 +/* DP_GUI_MASTER_CNTL DP_SRC_PITCH_OFFSET named constants */ +#define GMC_SRC_PITCH_OFFSET_CNTL_MASK 0x00000001 +#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 +#define GMC_SRC_PITCH_OFFSET_LEAVE_ALONE 0x00000001 + +/* DP_GUI_MASTER_CNTL DP_DST_PITCH_OFFSET named constants */ +#define GMC_DST_PITCH_OFFSET_CNTL_MASK 0x00000002 +#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 +#define GMC_DST_PITCH_OFFSET_LEAVE_ALONE 0x00000002 + /* DP_GUI_MASTER_CNTL DP_SRC_CLIPPING named constants */ #define GMC_SRC_CLIPPING_MASK 0x00000004 #define GMC_SRC_CLIP_DEFAULT 0x00000000 -- 2.51.0
