Hi, This series addes new instrucions and CPU model support for Intel Diamond Rapids.
This series mainly includes: * MOVRS CPUID * new AMX CPUIDs * AVX10.2 & AVX10_VNNI_INT * DMR CPU model & topology documentation This series is based on the previous minor cleanup: https://lore.kernel.org/qemu-devel/[email protected]/ And you can find the code here: https://gitlab.com/zhao.liu/qemu/-/tree/i386-all-for-dmr-v1.1-11-17-2025 One Thing More ============== I'm a bit unsure about the AVX10 model (patch 4). In principle, AVX10.1 should be allowed to run on an AVX10.2 host. For similarly version drived features, introducing a model might be a preferable way. However, PMU doesn't serve as a good example here. Thanks for your review! Best Regards, Zhao --- Zhao Liu (10): i386/cpu: Add support for MOVRS in CPUID enumeration i386/cpu: Add CPUID.0x1E.0x1 subleaf for AMX instructions i386/cpu: Add support for AVX10_VNNI_INT in CPUID enumeration i386/cpu: Support AVX10.2 with AVX10 feature models i386/cpu: Add a helper to get host avx10 version i386/cpu: Allow cache to be shared at thread level i386/cpu: Add an option in X86CPUDefinition to control CPUID 0x1f i386/cpu: Define dependency for VMX_VM_ENTRY_LOAD_IA32_FRED i386/cpu: Add CPU model for Diamond Rapids dosc/cpu-models-x86: Add documentation for DiamondRapids docs/system/cpu-models-x86.rst.inc | 20 ++ target/i386/cpu.c | 443 +++++++++++++++++++++++++---- target/i386/cpu.h | 27 ++ 3 files changed, 441 insertions(+), 49 deletions(-) -- 2.34.1
