On 11/20/25 10:47 PM, Nicolin Chen wrote:
> On Thu, Nov 20, 2025 at 01:22:09PM +0000, Shameer Kolothum wrote:
>> QEMU SMMUv3 currently sets the output address size (OAS) to 44 bits.
>> With accelerator mode enabled, a device may use SVA, where CPU page tables
>> are shared with the SMMU, requiring an OAS at least as large as the
>> CPU’s output address size. A user option is added to configure this.
>>
>> However, the OAS value advertised by the virtual SMMU must remain
>> compatible with the capabilities of the host SMMUv3. In accelerated
>> mode, the host SMMU performs stage-2 translation and must be able to
>> consume the intermediate physical addresses (IPA) produced by stage-1.
>>
>> The OAS exposed by the virtual SMMU defines the maximum IPA width that
>> stage-1 translations may generate. For AArch64 implementations, the
>> maximum usable IPA size on the host SMMU is determined by its own OAS.
>> Check that the configured OAS does not exceed what the host SMMU
>> can safely support.
>>
>> Tested-by: Zhangfei Gao <[email protected]>
>> Signed-off-by: Shameer Kolothum <[email protected]>
>> ---
>> hw/arm/smmuv3-accel.c | 20 ++++++++++++++++++++
>> hw/arm/smmuv3-internal.h | 3 ++-
>> hw/arm/smmuv3.c | 16 +++++++++++++++-
>> include/hw/arm/smmuv3.h | 1 +
>> 4 files changed, 38 insertions(+), 2 deletions(-)
>>
>> diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
>> index 73c7ce586a..35a94c720a 100644
>> --- a/hw/arm/smmuv3-accel.c
>> +++ b/hw/arm/smmuv3-accel.c
>> @@ -27,6 +27,12 @@
>> static MemoryRegion root, sysmem;
>> static AddressSpace *shared_as_sysmem;
>>
>> +static int smmuv3_oas_bits(uint32_t oas)
>> +{
>> + static const int map[] = { 32, 36, 40, 42, 44, 48, 52, 56 };
>> + return () ? map[oas] : -EINVAL;
> We should probably just:
> g_assert(oas < ARRAY_SIZE(map));
>
> -EINVAL is useless anyway in the caller that prints it.
>
> Otherwise,
>
> Reviewed-by: Nicolin Chen <[email protected]>
With Nicolin's suggestion
Reviewed-by: Eric Auger <[email protected]>
Eric
>
