On Fri, 13 Mar 2026 at 02:19, Lucas Amaral <[email protected]> wrote: > > Add a shared emulation library in target/arm/emulate/ using a > decodetree decoder (a64-ldst.decode) and a callback-based interface > (struct arm_emul_ops) that any hypervisor backend can implement. > > The hypervisor cannot emulate ISV=0 data aborts without decoding the > faulting instruction, since the ESR syndrome does not carry the access > size or target register. > > Signed-off-by: Lucas Amaral <[email protected]> > --- > target/arm/emulate/a64-ldst.decode | 293 ++++++++++++ > target/arm/emulate/arm_emulate.c | 738 +++++++++++++++++++++++++++++ > target/arm/emulate/arm_emulate.h | 55 +++ > target/arm/emulate/meson.build | 16 + > target/arm/meson.build | 1 + > 5 files changed, 1103 insertions(+)
This is a huge patch, please can you split it into more easily reviewable chunks? Something like "basic framework", then add the instructions in multiple patches that each cover one coherent group of insns. Are there any places where your decodetree file patterns differ from the tcg ones? If so, that's fine, but please note them in the relevant commit messages for convenience of review. thanks -- PMM
