The core GDB XML uses ABI names (zero, ra, sp, fp, ft0, fs0, etc.) but users also refer to registers by their numeric names (x0-x31, f0-f31) and the s0 alias for fp. The legacy MonitorDef mechanism supported both via split "x0/zero" name matching.
Register a feature that maps: - x0-x31 and s0 to the corresponding core integer registers - x0h-x31h and their ABI aliases (zeroh, rah, ...) to env->gprh[] - f0-f31 to the corresponding FPU registers (when FPU is present) CSR-by-name lookups ($mstatus, $sstatus, ...) keep working, through the existing GDB CSR feature rather than the removed csr_ops loop. Lookup is now case-sensitive (consistent with all other targets), including for the CSR names. Vector registers report "unknown register" instead of the target-specific "Unable to print the value of vector vreg" message. RV32 numeric and high-half aliases now zero-extend into HMP’s 64-bit expression value (for example, $x1 containing 0xffffffff evaluates to 4294967295, whereas the legacy fallback returned -1). This makes aliases consistent with the existing GDB-backed names. Signed-off-by: Marc-André Lureau <[email protected]> --- configs/targets/riscv32-linux-user.mak | 2 +- configs/targets/riscv32-softmmu.mak | 2 +- configs/targets/riscv64-bsd-user.mak | 2 +- configs/targets/riscv64-linux-user.mak | 2 +- configs/targets/riscv64-softmmu.mak | 2 +- gdbstub/gdb-xml/riscv-32bit-alias.xml | 105 ++++++++++++++++++++++ gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml | 40 +++++++++ gdbstub/gdb-xml/riscv-64bit-alias.xml | 105 ++++++++++++++++++++++ gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml | 46 ++++++++++ target/riscv/cpu.c | 1 - target/riscv/gdbstub.c | 48 ++++++++++ target/riscv/internals.h | 3 - target/riscv/monitor.c | 140 ------------------------------ 13 files changed, 349 insertions(+), 149 deletions(-) diff --git a/configs/targets/riscv32-linux-user.mak b/configs/targets/riscv32-linux-user.mak index d88fdf5e1b2f..8ee14fa14383 100644 --- a/configs/targets/riscv32-linux-user.mak +++ b/configs/targets/riscv32-linux-user.mak @@ -1,7 +1,7 @@ TARGET_ARCH=riscv32 TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv -TARGET_XML_FILES= riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-virtual.xml +TARGET_XML_FILES= riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-virtual.xml riscv-32bit-alias.xml riscv-32bit-fpu-alias.xml riscv-64bit-fpu-alias.xml CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y TARGET_SYSTBL_ABI=32 diff --git a/configs/targets/riscv32-softmmu.mak b/configs/targets/riscv32-softmmu.mak index 5d5016d00832..c717940344f0 100644 --- a/configs/targets/riscv32-softmmu.mak +++ b/configs/targets/riscv32-softmmu.mak @@ -1,6 +1,6 @@ TARGET_ARCH=riscv32 TARGET_BASE_ARCH=riscv -TARGET_XML_FILES= riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-virtual.xml +TARGET_XML_FILES= riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-virtual.xml riscv-32bit-alias.xml riscv-32bit-fpu-alias.xml riscv-64bit-fpu-alias.xml # needed by boot.c TARGET_NEED_FDT=y TARGET_LONG_BITS=32 diff --git a/configs/targets/riscv64-bsd-user.mak b/configs/targets/riscv64-bsd-user.mak index 5b4e138099fc..1d37e018c871 100644 --- a/configs/targets/riscv64-bsd-user.mak +++ b/configs/targets/riscv64-bsd-user.mak @@ -1,6 +1,6 @@ TARGET_ARCH=riscv64 TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv -TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml +TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml riscv-64bit-alias.xml riscv-32bit-fpu-alias.xml riscv-64bit-fpu-alias.xml TARGET_LONG_BITS=64 TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y diff --git a/configs/targets/riscv64-linux-user.mak b/configs/targets/riscv64-linux-user.mak index 35621520c560..564d15aaca8c 100644 --- a/configs/targets/riscv64-linux-user.mak +++ b/configs/targets/riscv64-linux-user.mak @@ -1,7 +1,7 @@ TARGET_ARCH=riscv64 TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv -TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml +TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml riscv-64bit-alias.xml riscv-32bit-fpu-alias.xml riscv-64bit-fpu-alias.xml CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y TARGET_SYSTBL_ABI=64 diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-softmmu.mak index a10dc03c04c8..28bfcdc575fb 100644 --- a/configs/targets/riscv64-softmmu.mak +++ b/configs/targets/riscv64-softmmu.mak @@ -1,7 +1,7 @@ TARGET_ARCH=riscv64 TARGET_BASE_ARCH=riscv TARGET_KVM_HAVE_GUEST_DEBUG=y -TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml riscv-32bit-cpu.xml riscv-32bit-virtual.xml +TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml riscv-32bit-cpu.xml riscv-32bit-virtual.xml riscv-32bit-alias.xml riscv-64bit-alias.xml riscv-32bit-fpu-alias.xml riscv-64bit-fpu-alias.xml # needed by boot.c TARGET_NEED_FDT=y TARGET_LONG_BITS=64 diff --git a/gdbstub/gdb-xml/riscv-32bit-alias.xml b/gdbstub/gdb-xml/riscv-32bit-alias.xml new file mode 100644 index 000000000000..a00a86ebdf95 --- /dev/null +++ b/gdbstub/gdb-xml/riscv-32bit-alias.xml @@ -0,0 +1,105 @@ +<?xml version="1.0"?> +<!-- + SPDX-License-Identifier: GPL-2.0-or-later +--> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.qemu.gdb.riscv.alias"> + <reg name="x0" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x1" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x2" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x3" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x4" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x5" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x6" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x7" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x8" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x9" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x10" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x11" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x12" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x13" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x14" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x15" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x16" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x17" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x18" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x19" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x20" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x21" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x22" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x23" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x24" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x25" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x26" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x27" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x28" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x29" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x30" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x31" bitsize="32" type="int" group="qemu-debug"/> + <reg name="s0" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x0h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="zeroh" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x1h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="rah" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x2h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="sph" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x3h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="gph" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x4h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="tph" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x5h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="t0h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x6h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="t1h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x7h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="t2h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x8h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="s0h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x9h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="s1h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x10h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="a0h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x11h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="a1h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x12h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="a2h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x13h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="a3h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x14h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="a4h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x15h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="a5h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x16h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="a6h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x17h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="a7h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x18h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="s2h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x19h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="s3h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x20h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="s4h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x21h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="s5h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x22h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="s6h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x23h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="s7h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x24h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="s8h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x25h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="s9h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x26h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="s10h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x27h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="s11h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x28h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="t3h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x29h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="t4h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x30h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="t5h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="x31h" bitsize="32" type="int" group="qemu-debug"/> + <reg name="t6h" bitsize="32" type="int" group="qemu-debug"/> +</feature> diff --git a/gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml b/gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml new file mode 100644 index 000000000000..3935f72ea289 --- /dev/null +++ b/gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml @@ -0,0 +1,40 @@ +<?xml version="1.0"?> +<!-- + SPDX-License-Identifier: GPL-2.0-or-later +--> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.qemu.gdb.riscv.fpu-alias"> + <reg name="f0" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f1" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f2" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f3" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f4" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f5" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f6" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f7" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f8" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f9" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f10" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f11" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f12" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f13" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f14" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f15" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f16" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f17" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f18" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f19" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f20" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f21" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f22" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f23" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f24" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f25" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f26" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f27" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f28" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f29" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f30" bitsize="32" type="ieee_single" group="qemu-debug"/> + <reg name="f31" bitsize="32" type="ieee_single" group="qemu-debug"/> +</feature> diff --git a/gdbstub/gdb-xml/riscv-64bit-alias.xml b/gdbstub/gdb-xml/riscv-64bit-alias.xml new file mode 100644 index 000000000000..28781b230226 --- /dev/null +++ b/gdbstub/gdb-xml/riscv-64bit-alias.xml @@ -0,0 +1,105 @@ +<?xml version="1.0"?> +<!-- + SPDX-License-Identifier: GPL-2.0-or-later +--> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.qemu.gdb.riscv.alias"> + <reg name="x0" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x1" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x2" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x3" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x4" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x5" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x6" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x7" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x8" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x9" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x10" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x11" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x12" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x13" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x14" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x15" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x16" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x17" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x18" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x19" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x20" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x21" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x22" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x23" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x24" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x25" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x26" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x27" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x28" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x29" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x30" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x31" bitsize="64" type="int" group="qemu-debug"/> + <reg name="s0" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x0h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="zeroh" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x1h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="rah" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x2h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="sph" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x3h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="gph" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x4h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="tph" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x5h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="t0h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x6h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="t1h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x7h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="t2h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x8h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="s0h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x9h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="s1h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x10h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="a0h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x11h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="a1h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x12h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="a2h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x13h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="a3h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x14h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="a4h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x15h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="a5h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x16h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="a6h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x17h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="a7h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x18h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="s2h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x19h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="s3h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x20h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="s4h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x21h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="s5h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x22h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="s6h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x23h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="s7h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x24h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="s8h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x25h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="s9h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x26h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="s10h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x27h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="s11h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x28h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="t3h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x29h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="t4h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x30h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="t5h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="x31h" bitsize="64" type="int" group="qemu-debug"/> + <reg name="t6h" bitsize="64" type="int" group="qemu-debug"/> +</feature> diff --git a/gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml b/gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml new file mode 100644 index 000000000000..13e6b341a0f8 --- /dev/null +++ b/gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml @@ -0,0 +1,46 @@ +<?xml version="1.0"?> +<!-- + SPDX-License-Identifier: GPL-2.0-or-later +--> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.qemu.gdb.riscv.fpu-alias"> + + <union id="riscv_double"> + <field name="float" type="ieee_single"/> + <field name="double" type="ieee_double"/> + </union> + + <reg name="f0" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f1" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f2" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f3" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f4" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f5" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f6" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f7" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f8" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f9" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f10" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f11" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f12" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f13" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f14" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f15" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f16" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f17" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f18" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f19" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f20" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f21" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f22" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f23" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f24" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f25" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f26" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f27" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f28" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f29" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f30" bitsize="64" type="riscv_double" group="qemu-debug"/> + <reg name="f31" bitsize="64" type="riscv_double" group="qemu-debug"/> +</feature> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 08a4d14ea1f6..7b052da6d8b4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3107,7 +3107,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = { .legacy_vmsd = &vmstate_riscv_cpu, #ifdef CONFIG_TCG .translate_for_debug = riscv_cpu_translate_for_debug, - .monitor_get_register = riscv_monitor_get_register_legacy, #endif }; #endif diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index f279f4ab2461..0d89caf8ba36 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -336,10 +336,42 @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg) return &cpu->dyn_vreg_feature; } +/* x0-x31, s0, then pairs of numeric and ABI high-half aliases. */ +static int riscv_gdb_get_alias(CPUState *cs, GByteArray *buf, int n) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + uint64_t val; + + if (n < 33) { + return riscv_cpu_gdb_read_register(cs, buf, n == 32 ? 8 : n); + } + + val = cpu->env.gprh[(n - 33) / 2]; + if (riscv_cpu_is_32bit(cpu)) { + return gdb_get_reg32(buf, val); + } + return gdb_get_reg64(buf, val); +} + +static int riscv_gdb_set_alias(CPUState *cs, uint8_t *buf, int n) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + const unsigned regsz = riscv_cpu_is_32bit(cpu) ? 4 : 8; + + if (n < 33) { + return riscv_cpu_gdb_write_register(cs, buf, n == 32 ? 8 : n); + } + + env->gprh[(n - 33) / 2] = ldn(env, buf, regsz); + return regsz; +} + void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; + if (env->misa_ext & RVD) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, gdb_find_static_feature("riscv-64bit-fpu.xml")); @@ -380,4 +412,20 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) feature); } #endif + + gdb_register_internal_coprocessor( + cs, riscv_gdb_get_alias, riscv_gdb_set_alias, + gdb_find_static_feature(riscv_cpu_is_32bit(cpu) ? + "riscv-32bit-alias.xml" : + "riscv-64bit-alias.xml")); + + if (env->misa_ext & RVD) { + gdb_register_internal_coprocessor( + cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, + gdb_find_static_feature("riscv-64bit-fpu-alias.xml")); + } else if (env->misa_ext & RVF) { + gdb_register_internal_coprocessor( + cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, + gdb_find_static_feature("riscv-32bit-fpu-alias.xml")); + } } diff --git a/target/riscv/internals.h b/target/riscv/internals.h index f17d011d22fb..f4af4636c6ca 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -265,7 +265,4 @@ static inline int insn_len(uint16_t first_word) return (first_word & 3) == 3 ? 4 : 2; } -int riscv_monitor_get_register_legacy(CPUState *cs, const char *name, - int64_t *pval); - #endif diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index 7e61ae2a4717..20f3ba57ae57 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -19,10 +19,7 @@ */ #include "qemu/osdep.h" -#include "qemu/ctype.h" -#include "qemu/qemu-print.h" #include "cpu.h" -#include "target/riscv/tcg/csr.h" #include "cpu_bits.h" #include "monitor/monitor.h" #include "monitor/hmp.h" @@ -247,140 +244,3 @@ void hmp_info_mem(MonitorHMP *hmp, const QDict *qdict) mem_info_svxx(hmp, env); } #endif /* CONFIG_HMP */ - -#ifdef CONFIG_TCG -static bool reg_is_ulong_integer(CPURISCVState *env, const char *name, - target_ulong *val, bool is_gprh) -{ - const char * const *reg_names; - uint64_t *vals; - - if (is_gprh) { - reg_names = riscv_int_regnamesh; - vals = env->gprh; - } else { - reg_names = riscv_int_regnames; - vals = env->gpr; - } - - for (int i = 0; i < 32; i++) { - g_auto(GStrv) reg_name = g_strsplit(reg_names[i], "/", 2); - - g_assert(reg_name[0]); - g_assert(reg_name[1]); - - if (g_ascii_strcasecmp(reg_name[0], name) == 0 || - g_ascii_strcasecmp(reg_name[1], name) == 0) { - *val = vals[i]; - return true; - } - } - - return false; -} - -static bool reg_is_u64_fpu(CPURISCVState *env, const char *name, uint64_t *val) -{ - if (qemu_tolower(name[0]) != 'f') { - return false; - } - - for (int i = 0; i < 32; i++) { - g_auto(GStrv) reg_name = g_strsplit(riscv_fpr_regnames[i], "/", 2); - - g_assert(reg_name[0]); - g_assert(reg_name[1]); - - if (g_ascii_strcasecmp(reg_name[0], name) == 0 || - g_ascii_strcasecmp(reg_name[1], name) == 0) { - *val = env->fpr[i]; - return true; - } - } - - return false; -} - -static bool reg_is_vreg(const char *name) -{ - if (qemu_tolower(name[0]) != 'v' || strlen(name) > 3) { - return false; - } - - for (int i = 0; i < 32; i++) { - if (g_ascii_strcasecmp(name, riscv_rvv_regnames[i]) == 0) { - return true; - } - } - - return false; -} - -int riscv_monitor_get_register_legacy(CPUState *cs, const char *name, - int64_t *pval) -{ - RISCVCPU *hart = RISCV_CPU(cs); - CPURISCVState *env = cpu_env(cs); - target_ulong val = 0; - uint64_t val64 = 0; - int i; - - if (reg_is_ulong_integer(env, name, &val, false) || - reg_is_ulong_integer(env, name, &val, true)) { - *pval = riscv_cpu_is_32bit(hart) ? (int32_t)val : val; - return 0; - } - - if (reg_is_u64_fpu(env, name, &val64)) { - *pval = val64; - return 0; - } - - if (reg_is_vreg(name)) { - if (!riscv_cpu_cfg(env)->ext_zve32x) { - return -EINVAL; - } - - qemu_printf("Unable to print the value of vector " - "vreg '%s' from this API\n", name); - - /* - * We're returning 0 because returning -EINVAL triggers - * an 'unknown register' message in exp_unary() later, - * which feels ankward after our own error message. - */ - *pval = 0; - return 0; - } - - for (i = 0; i < ARRAY_SIZE(csr_ops); i++) { - RISCVException res; - int csrno = i; - - /* - * Early skip when possible since we're going - * through a lot of NULL entries. - */ - if (csr_ops[csrno].predicate == NULL) { - continue; - } - - if (g_ascii_strcasecmp(csr_ops[csrno].name, name) != 0) { - continue; - } - - res = riscv_csrrw_debug(env, csrno, &val, 0, 0); - - /* - * Rely on the smode, hmode, etc, predicates within csr.c - * to do the filtering of the registers that are present. - */ - if (res == RISCV_EXCP_NONE) { - *pval = riscv_cpu_is_32bit(hart) ? (int32_t)val : val; - return 0; - } - } - - return -EINVAL; -} -#endif -- 2.56.0.116.g6de20f6092dc
