On Thu, 2026-10-22 at 20:59 +0100, Peter Maydell wrote: > FLEXCAN_CRC_MBCRC is defined as > (((x) & FLEXCAN_CRCR_MBCRC_MASK) << 16) > but FLEXCAN_CRCRC_MBCRC_MASK is (like the other _MASK values > in this header) defined to be an in-place mask > FLEXCAN_GENMASK(22, 16) > (a value with bits set from 16 to 22). The mask and shift operations > are done in the wrong order, and so the result of the macro can only > ever be zero. > > Fix the macro to shift first and mask second. > > Cc: [email protected] > Fixes: 3c4e23cbb597 ("hw/net/can/flexcan: NXP FlexCAN core > emulation") > Resolves: Coverity CID 1662973 > Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Matyas Bobek <[email protected]> Thanks, Matt
