Am 29.06.2013 22:01, schrieb Andreas Färber:
> diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
> index 01d4bbf..86aad6a 100644
> --- a/target-microblaze/helper.c
> +++ b/target-microblaze/helper.c
> @@ -152,7 +152,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
> "hw exception at pc=%x ear=%x esr=%x iflags=%x\n",
> env->sregs[SR_PC], env->sregs[SR_EAR],
> env->sregs[SR_ESR], env->iflags);
> - log_cpu_state_mask(CPU_LOG_INT, env, 0);
> + log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), 0);
> env->iflags &= ~(IMM_FLAG | D_FLAG);
> env->sregs[SR_PC] = cpu->base_vectors + 0x20;
> break;
> @@ -175,7 +175,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
> "bimm exception at pc=%x iflags=%x\n",
> env->sregs[SR_PC], env->iflags);
> env->regs[17] -= 4;
> - log_cpu_state_mask(CPU_LOG_INT, env, 0);
> + log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), 0);
> }
> } else if (env->iflags & IMM_FLAG) {
> D(qemu_log("IMM_FLAG set at exception\n"));
> @@ -192,7 +192,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
> qemu_log_mask(CPU_LOG_INT,
> "exception at pc=%x ear=%x iflags=%x\n",
> env->sregs[SR_PC], env->sregs[SR_EAR],
> env->iflags);
> - log_cpu_state_mask(CPU_LOG_INT, env, 0);
> + log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), 0);
> env->iflags &= ~(IMM_FLAG | D_FLAG);
> env->sregs[SR_PC] = cpu->base_vectors + 0x20;
> break;
> @@ -222,7 +222,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
> env->sregs[SR_PC], env->sregs[SR_MSR], t,
> env->iflags,
> sym);
>
> - log_cpu_state(env, 0);
> + log_cpu_state(CPU(cpu), 0);
> }
> }
> #endif
> @@ -236,7 +236,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
>
> env->regs[14] = env->sregs[SR_PC];
> env->sregs[SR_PC] = cpu->base_vectors + 0x10;
> - //log_cpu_state_mask(CPU_LOG_INT, env, 0);
> + //log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), 0);
> break;
>
> case EXCP_BREAK:
> @@ -247,7 +247,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
> qemu_log_mask(CPU_LOG_INT,
> "break at pc=%x msr=%x %x iflags=%x\n",
> env->sregs[SR_PC], env->sregs[SR_MSR], t,
> env->iflags);
> - log_cpu_state_mask(CPU_LOG_INT, env, 0);
> + log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), 0);
> env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
> env->sregs[SR_MSR] |= t;
> env->sregs[SR_MSR] |= MSR_BIP;
Re-reviewing this patch for my X86CPU changes, I noticed all these could
use "cs" rather than "CPU(cpu)" - fixed and applied along with the
following one to qom-cpu:
https://github.com/afaerber/qemu-cpu/commits/qom-cpu
> diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
> index 54f439f..f9acdb1 100644
> --- a/target-microblaze/translate.c
> +++ b/target-microblaze/translate.c
> @@ -1741,6 +1741,9 @@ static void
> gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb,
> int search_pc)
> {
> +#if !SIM_COMPAT
> + MicroBlazeCPU *cpu = mb_env_get_cpu(env);
> +#endif
> uint16_t *gen_opc_end;
> uint32_t pc_start;
> int j, lj;
[snip]
This hunk would benefit from the gen_intermediate_code_internal()
argument type change prompted by gdbstub later in this series, so I
intend to prepend those once v2 is done - inline is missing here.
Trying to avoid resending a 41-patch series. ;)
TBD: Follow up with patches for the x86 and ppc logging macros
respectively before I forget about them.
Andreas
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