On Thu, May 08, 2014 at 12:45:03PM +1000, Peter Crosthwaite wrote: > On Thu, May 8, 2014 at 11:35 AM, Edgar E. Iglesias > <[email protected]> wrote: > > From: Guenter Roeck <[email protected]> > > > > The TCSR register has only 11 valid bits. This is now used by the > > linux kernel to auto-detect endianness, and causes Linux 3.15-rc1 > > and later to hang when run under qemu-microblaze. Mask valid bits > > before writing the register to solve the problem. > > > > Signed-off-by: Guenter Roeck <[email protected]> > > Reviewed-by: Edgar E. Iglesias <[email protected]> > > Signed-off-by: Edgar E. Iglesias <[email protected]> > > --- > > hw/timer/xilinx_timer.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c > > index 6113b97..3ff1da9 100644 > > --- a/hw/timer/xilinx_timer.c > > +++ b/hw/timer/xilinx_timer.c > > @@ -169,7 +169,7 @@ timer_write(void *opaque, hwaddr addr, > > if (value & TCSR_TINT) > > value &= ~TCSR_TINT; > > > > - xt->regs[addr] = value; > > + xt->regs[addr] = value & 0x7ff; > > In at least the later TRMs, Bit 11 is validly defined as the cascade > bit, taking the total number of bits to 12. I think this mask should > be 0xfff.
Hi, For timer versions without cascading support, bit 11 is reserved. I think the patch is good. Once someone adds cascading support we can expose and implement the cascading bit + the necessary additional regs. Cheers, Edgar
