> That's what tb->flags and env->hflags. An encoding of cpu state at translation time.
Can you please add more thoughts on this? Within the same translation block, we can have an instruction that alters HWrena (mtc0) and rdwhr instruction that will behave differently based on content of HWrena. P. ________________________________________ From: Richard Henderson [rth7...@gmail.com] on behalf of Richard Henderson [r...@twiddle.net] Sent: Tuesday, May 27, 2014 4:38 AM To: Petar Jovanovic; Petar Jovanovic; qemu-devel@nongnu.org Cc: aurel...@aurel32.net; James Hogan Subject: Re: [v2 PATCH] target-mips: implement UserLocal Register On 05/26/2014 07:32 PM, Petar Jovanovic wrote: > > ________________________________________ > From: Richard Henderson [rth7...@gmail.com] on behalf of Richard Henderson > [r...@twiddle.net] > Sent: Tuesday, May 27, 2014 3:35 AM > To: Petar Jovanovic; Petar Jovanovic; qemu-devel@nongnu.org > Cc: aurel...@aurel32.net; James Hogan > Subject: Re: [v2 PATCH] target-mips: implement UserLocal Register > > On 05/26/2014 06:21 PM, Petar Jovanovic wrote: >> Because we do not know the content of CP0_HWREna. > >> We can know the same way we know the content of CP0_Config3. > > Almost all the bits in CP0_Config3 including ULRI bit are read-only and > preset by > hardware, thus checking bit ULRI at translation time is the same as checking > it > at execution time. How can we know the content of CP0_HWREna at translation > time? That's what tb->flags and env->hflags. An encoding of cpu state at translation time. r~
