From: Fabian Aggeler <aggel...@ethz.ch>
Implements NSACR register with corresponding read/write functions
for ARMv7 and ARMv8.
Signed-off-by: Sergey Fedorov <s.fedo...@samsung.com>
Signed-off-by: Fabian Aggeler <aggel...@ethz.ch>
Signed-off-by: Greg Bellows <greg.bell...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
---
v8 -> v9
- Removed unused NSACR constants
- Added TODO for trapping secure EL1 accesses to NSACR
- Change NSACR access from PL3_RW to PL3_W
- Fixed declaration order of the NSACR register components
v7 -> v8
- Update naming from c1_nsacr to nsacr to match other registers being changed.
- Remove NSACR read/write functions
v4 -> v5
- Changed to use renamed arm_current_el()
---
target-arm/cpu.h | 1 +
target-arm/helper.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index baa709b..97f952c 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -181,6 +181,7 @@ typedef struct CPUARMState {
uint64_t c1_sys; /* System control register. */
uint64_t c1_coproc; /* Coprocessor access register. */
uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
+ uint32_t nsacr; /* Non-secure access control register. */
uint64_t ttbr0_el1; /* MMU translation table base 0. */
uint64_t ttbr1_el1; /* MMU translation table base 1. */
uint64_t c2_control; /* MMU translation table base control. */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3086c2c..016cf39 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2344,6 +2344,10 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
.cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
.access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState,
cp15.scr_el3),
.resetfn = arm_cp_reset_ignore, .writefn = scr_write },
+ /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
+ { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
+ .access = PL3_W | PL1_R, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.nsacr) },
REGINFO_SENTINEL
};
--
1.8.3.2
