On Mon, Mar 15, 2010 at 12:53:25PM +0000, Paul Brook wrote:
> > +#if !defined(CONFIG_USER_ONLY)
> > if (arm_feature(env, ARM_FEATURE_XSCALE)
> > && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum)))
> > return 1;
> > +#endif
>
> This is almost certainly the wrong way to fix this.
>
> Paul
>
Here is a different fix. Hopefully I am on the right track this time. This
patch inits the cpu to have CP0 and/or CP1 accessible from the beginning if in
linux-user mode.
Signed-off-by: Lars Munch <l...@segv.dk>
---
target-arm/helper.c | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 1a181ac..3a55da2 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -165,6 +165,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t
id)
/* JTAG_ID is ((id << 28) | 0x09265013) */
env->cp15.c0_cachetype = 0xd172172;
env->cp15.c1_sys = 0x00000078;
+#if defined (CONFIG_USER_ONLY)
+ env->cp15.c15_cpar = 0x00000001;
+#endif
break;
case ARM_CPUID_PXA270_A0:
case ARM_CPUID_PXA270_A1:
@@ -178,6 +181,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t
id)
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
env->cp15.c0_cachetype = 0xd172172;
env->cp15.c1_sys = 0x00000078;
+#if defined (CONFIG_USER_ONLY)
+ env->cp15.c15_cpar = 0x00000003;
+#endif
break;
default:
cpu_abort(env, "Bad CPU ID: %x\n", id);
--
1.7.0
