Peter Maydell <peter.mayd...@linaro.org> writes: > On 28 January 2015 at 15:57, Peter Maydell <peter.mayd...@linaro.org> wrote: >> On 28 January 2015 at 15:54, Alex Bennée <alex.ben...@linaro.org> wrote: >>> Do we have test cases that trip up here? It would be nice to include >>> them in our testing as the random nature of RISU has obviously failed to >>> trip up on this instruction. >> >> Risu would probably catch this if we generated and ran test cases >> which set the FPSCR bits to something other than the default. > > This bug is indeed caught by the following risugen: > ./risugen --numinsns 10000 --pattern "FMULX A64_V" --fpscr 0x01000000 > aarch64.risu FMULX_S3SAME_V_squash.out > > (that fpscr value being "set DZ, nothing else".) > > Alex, I don't suppose your automation of these tests makes > it easy to do a complete extra run (or better, just of the > Neon and FP insn tests) with different FPSCR flags?
I just need to add the additional test sequence and trace to the tarball and the script should pick it up automatically. > > -- PMM -- Alex Bennée
