On Thu, 14 May 2015, Leon Alrae wrote: > > I don't think we have. The specification is a bit unclear I must admit > > and it also defines the details of vector load and store operations as > > implementation dependent, so there's no further clarification. > > This is specified in "MIPS Architecture For Programmers Volume I-A: > Introduction to the MIPS64 Architecture", Revision: 6.01, Imagination > Technologies, Document Number: MD00083, August 20, 2014, p.142: > > "For example, a misaligned vector load instruction will never leave its > vector destination register half written, if part of a page split > succeeds and the other part takes an exception. It is either all done, > or not at all."
Thanks. It's good to see r6 has clarified the matters around here and I think we can (and for simplicity ought to) apply them to r5 too. Maciej
