Hi Peter and all, This patch series adds ARM Cortex R5 processor support. The PMSAv7 MPU is implemented. Two R5s are added to the Xilinx ZynqMP SoC.
Regards, Peter Peter Crosthwaite (9): target-arm: Prepare support for Cortex-R5 arm: helper: Factor out CP regs common to [pv]msa target-arm/helper.c: define MPUIR register target-arm: Add registers for PMSAv7 arm: helper: rename get_phys_addr_mpu target-arm: Implement PMSAv7 MPU arm: r5: Implement dummy ATCM, BTCM and D-cache invalidate arm: xlnx-zynqmp: Preface CPU variables with "A" arm: xlnx-zynqmp: Add 2xCortexR5 CPUs hw/arm/xlnx-ep108.c | 2 +- hw/arm/xlnx-zynqmp.c | 50 +++++++--- include/hw/arm/xlnx-zynqmp.h | 6 +- target-arm/cpu.c | 39 ++++++++ target-arm/cpu.h | 9 ++ target-arm/helper.c | 226 +++++++++++++++++++++++++++++++++++++++---- 6 files changed, 299 insertions(+), 33 deletions(-) -- 2.4.2.3.g2ffcb72
