On 1 June 2015 at 19:04, Peter Crosthwaite <peter.crosthwa...@xilinx.com> wrote:
> Just hardcoded to 16way unified MPU.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
> ---
> target-arm/cpu.h | 2 ++
> target-arm/helper.c | 4 ++++
> 2 files changed, 6 insertions(+)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 21b5b8e..09cc16d 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -115,6 +115,8 @@ typedef struct ARMGenericTimer {
> #define GTIMER_VIRT 1
> #define NUM_GTIMERS 2
>
> +#define PMSAV7_MPU_NUM_REGIONS 16
> +
> typedef struct {
> uint64_t raw_tcr;
> uint32_t mask;
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 78b6406..cb21bbf 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -3387,6 +3387,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> { .name = "TLBTR",
> .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
> .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
> + { .name = "MPUIR",
> + .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = PMSAV7_MPU_NUM_REGIONS << 8 },
> REGINFO_SENTINEL
> };
> ARMCPRegInfo crn0_wi_reginfo = {
Isn't this going to define the register for VMSA as well?
-- PMM
