On 7 July 2015 at 19:25, Alex Zuepke <alexander.zue...@hs-rm.de> wrote: > This patch series enables MPU support for Cortex-M3/M4 devices, > based on the existing MPU support for Cortex-R series in QEMU. > The MPU supports a variable number of windows and default to 8, the current > limit on most Cortex-M3/M4 devices. Also, the necessary registers for > exception handling and fault decoding are implemented. > Like on Cortex-R5, the MPU can be turned off by setting "pmsav7-dregion" to > zero.
Cool -- very nice to see this gap in our feature set filled in. With hardfreeze today it might take me a little time to get to reviewing this but it is on my list. thanks -- PMM
