This reserves one PPI (private peripheral interrupt) for the PMU and creates a corresponding entry in the device tree.
Writteb by Aaron Lindsay. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- hw/arm/virt.c | 21 +++++++++++++++++++++ target-arm/cpu-qom.h | 4 ++-- target-arm/cpu.c | 8 ++++---- target-arm/cpu.h | 3 ++- target-arm/helper.c | 6 +++--- 5 files changed, 32 insertions(+), 10 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 565f573..bd1fbb6 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -295,6 +295,23 @@ static void fdt_add_timer_nodes(const VirtBoardInfo *vbi) GIC_FDT_IRQ_TYPE_PPI, 10, irqflags); } +static void fdt_add_pmu_nodes(const VirtBoardInfo *vbi) +{ + uint32_t irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; + const char nodename[] = "/pmu"; + const char compat[] = "arm,armv8-pmuv3\0arm,cortex-a15-pmu"; + + irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, + GIC_FDT_IRQ_PPI_CPU_WIDTH, (1 << vbi->smp_cpus) - 1); + + + qemu_fdt_add_subnode(vbi->fdt, nodename); + qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat)); + + qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", + GIC_FDT_IRQ_TYPE_PPI, 7, irqflags); +} + static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi) { int cpu; @@ -384,6 +401,9 @@ static uint32_t create_gic(const VirtBoardInfo *vbi, qemu_irq *pic) /* virtual timer */ qdev_connect_gpio_out(cpudev, 1, qdev_get_gpio_in(gicdev, ppibase + 27)); + /* PMU */ + qdev_connect_gpio_out(cpudev, 2, + qdev_get_gpio_in(gicdev, ppibase + 23)); sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); } @@ -802,6 +822,7 @@ static void machvirt_init(MachineState *machine) } g_strfreev(cpustr); fdt_add_timer_nodes(vbi); + fdt_add_pmu_nodes(vbi); fdt_add_cpu_nodes(vbi); fdt_add_psci_node(vbi); diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index ed5a644..bb6722f 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -84,8 +84,8 @@ typedef struct ARMCPU { /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; - /* GPIO outputs for generic timer */ - qemu_irq gt_timer_outputs[NUM_GTIMERS]; + /* GPIO outputs for generic timer and PMU */ + qemu_irq ppi_outputs[NUM_GTIMERS + 1]; /* 'compatible' string for this CPU for Linux device trees */ const char *dtb_compatible; diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 3ca3fa8..87d0772 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -379,17 +379,17 @@ static void arm_cpu_initfn(Object *obj) /* VIRQ and VFIQ are unused with KVM but we add them to maintain * the same interface as non-KVM CPUs. */ - qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); + qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 5); } else { - qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); + qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 5); } cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, arm_gt_ptimer_cb, cpu); cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, arm_gt_vtimer_cb, cpu); - qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, - ARRAY_SIZE(cpu->gt_timer_outputs)); + qdev_init_gpio_out(DEVICE(cpu), cpu->ppi_outputs, + ARRAY_SIZE(cpu->ppi_outputs)); #endif /* DTB consumers generally don't in fact care what the 'compatible' diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 2525569..44084a5 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -112,9 +112,10 @@ typedef struct ARMGenericTimer { uint64_t ctl; /* Timer Control register */ } ARMGenericTimer; +#define NUM_GTIMERS 2 #define GTIMER_PHYS 0 #define GTIMER_VIRT 1 -#define NUM_GTIMERS 2 +#define PMU_IDX 2 typedef struct { uint64_t raw_tcr; diff --git a/target-arm/helper.c b/target-arm/helper.c index d2c02be..1843ec5 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1216,7 +1216,7 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) uint64_t nexttick; gt->ctl = deposit32(gt->ctl, 2, 1, istatus); - qemu_set_irq(cpu->gt_timer_outputs[timeridx], + qemu_set_irq(cpu->ppi_outputs[timeridx], (istatus && !(gt->ctl & 2))); if (istatus) { /* Next transition is when count rolls back over to zero */ @@ -1237,7 +1237,7 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) } else { /* Timer disabled: ISTATUS and timer output always clear */ gt->ctl &= ~4; - qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); + qemu_set_irq(cpu->ppi_outputs[timeridx], 0); timer_del(cpu->gt_timer[timeridx]); } } @@ -1297,7 +1297,7 @@ static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, /* IMASK toggled: don't need to recalculate, * just set the interrupt line based on ISTATUS */ - qemu_set_irq(cpu->gt_timer_outputs[timeridx], + qemu_set_irq(cpu->ppi_outputs[timeridx], (oldval & 4) && !(value & 2)); } } -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project