The ADD IMMEDIATE instructions are in the extended-immediate facility.
Using them gives us a 32-bit immediate addend.
Signed-off-by: Richard Henderson <r...@twiddle.net>
---
tcg/s390/tcg-target.c | 96 ++++++++++++++++++++++++++++++++++++++++--------
1 files changed, 80 insertions(+), 16 deletions(-)
diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
index 826a2c8..795ddcd 100644
--- a/tcg/s390/tcg-target.c
+++ b/tcg/s390/tcg-target.c
@@ -33,8 +33,9 @@
do { } while (0)
#endif
-#define TCG_CT_CONST_S16 0x100
-#define TCG_CT_CONST_U12 0x200
+#define TCG_CT_CONST_32 0x100
+#define TCG_CT_CONST_NEG 0x200
+#define TCG_CT_CONST_ADDI 0x400
/* Several places within the instruction set 0 means "no register"
rather than TCG_REG_R0. */
@@ -49,6 +50,9 @@
halves of the 16-bit quantity may appear 32 bits apart in the insn.
This makes it easy to copy the values from the tables in Appendix B. */
typedef enum S390Opcode {
+ RIL_AFI = 0xc209,
+ RIL_AGFI = 0xc208,
+ RIL_ALGFI = 0xc20a,
RIL_BRASL = 0xc005,
RIL_BRCL = 0xc004,
RIL_LARL = 0xc000,
@@ -303,9 +307,17 @@ static int target_parse_constraint(TCGArgConstraint *ct,
const char **pct_str)
tcg_regset_clear(ct->u.regs);
tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);
break;
+ case 'N': /* force immediate negate */
+ ct->ct &= ~TCG_CT_REG;
+ ct->ct |= TCG_CT_CONST_NEG;
+ break;
+ case 'W': /* force 32-bit ("word") immediate */
+ ct->ct &= ~TCG_CT_REG;
+ ct->ct |= TCG_CT_CONST_32;
+ break;
case 'I':
ct->ct &= ~TCG_CT_REG;
- ct->ct |= TCG_CT_CONST_S16;
+ ct->ct |= TCG_CT_CONST_ADDI;
break;
default:
break;
@@ -322,12 +334,31 @@ static inline int tcg_target_const_match(tcg_target_long
val,
{
int ct = arg_ct->ct;
- if ((ct & TCG_CT_CONST) ||
- ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) ||
- ((ct & TCG_CT_CONST_U12) && val == (val & 0xfff))) {
+ if (ct & TCG_CT_CONST) {
return 1;
}
+ /* Handle the modifiers. */
+ if (ct & TCG_CT_CONST_NEG) {
+ val = -val;
+ }
+ if (ct & TCG_CT_CONST_32) {
+ val = (int32_t)val;
+ }
+
+ /* The following are mutually exclusive. */
+ if (ct & TCG_CT_CONST_ADDI) {
+ /* Immediates that may be used with add. If we have the
+ extended-immediates facility then we have ADD IMMEDIATE
+ with signed and unsigned 32-bit, otherwise we have only
+ ADD HALFWORD IMMEDIATE with a signed 16-bit. */
+ if (facilities & FACILITY_EXT_IMM) {
+ return val == (int32_t)val || val == (uint32_t)val;
+ } else {
+ return val == (int16_t)val;
+ }
+ }
+
return 0;
}
@@ -649,6 +680,29 @@ static inline void tgen_ext32u(TCGContext *s, TCGReg dest,
TCGReg src)
tcg_out_insn(s, RRE, LLGFR, dest, src);
}
+static void tgen32_addi(TCGContext *s, TCGReg dest, int32_t val)
+{
+ if (val == (int16_t)val) {
+ tcg_out_insn(s, RI, AHI, dest, val);
+ } else {
+ tcg_out_insn(s, RIL, AFI, dest, val);
+ }
+}
+
+static void tgen64_addi(TCGContext *s, TCGReg dest, int64_t val)
+{
+ if (val == (int16_t)val) {
+ tcg_out_insn(s, RI, AGHI, dest, val);
+ } else if (val == (int32_t)val) {
+ tcg_out_insn(s, RIL, AGFI, dest, val);
+ } else if (val == (uint32_t)val) {
+ tcg_out_insn(s, RIL, ALGFI, dest, val);
+ } else {
+ tcg_abort();
+ }
+
+}
+
static void tgen32_cmp(TCGContext *s, TCGCond c, TCGReg r1, TCGReg r2)
{
if (c > TCG_COND_GT) {
@@ -1095,22 +1149,32 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
case INDEX_op_add_i32:
if (const_args[2]) {
- tcg_out_insn(s, RI, AHI, args[0], args[2]);
+ tgen32_addi(s, args[0], args[2]);
} else {
tcg_out_insn(s, RR, AR, args[0], args[2]);
}
break;
-
case INDEX_op_add_i64:
- tcg_out_insn(s, RRE, AGR, args[0], args[2]);
+ if (const_args[2]) {
+ tgen64_addi(s, args[0], args[2]);
+ } else {
+ tcg_out_insn(s, RRE, AGR, args[0], args[2]);
+ }
break;
case INDEX_op_sub_i32:
- tcg_out_insn(s, RR, SR, args[0], args[2]);
+ if (const_args[2]) {
+ tgen32_addi(s, args[0], -args[2]);
+ } else {
+ tcg_out_insn(s, RR, SR, args[0], args[2]);
+ }
break;
-
case INDEX_op_sub_i64:
- tcg_out_insn(s, RRE, SGR, args[0], args[2]);
+ if (const_args[2]) {
+ tgen64_addi(s, args[0], -args[2]);
+ } else {
+ tcg_out_insn(s, RRE, SGR, args[0], args[2]);
+ }
break;
case INDEX_op_and_i32:
@@ -1383,8 +1447,8 @@ static const TCGTargetOpDef s390_op_defs[] = {
{ INDEX_op_st16_i32, { "r", "r" } },
{ INDEX_op_st_i32, { "r", "r" } },
- { INDEX_op_add_i32, { "r", "0", "rI" } },
- { INDEX_op_sub_i32, { "r", "0", "r" } },
+ { INDEX_op_add_i32, { "r", "0", "rWI" } },
+ { INDEX_op_sub_i32, { "r", "0", "rWNI" } },
{ INDEX_op_mul_i32, { "r", "0", "r" } },
{ INDEX_op_div2_i32, { "b", "a", "0", "1", "r" } },
@@ -1444,8 +1508,8 @@ static const TCGTargetOpDef s390_op_defs[] = {
{ INDEX_op_st32_i64, { "r", "r" } },
{ INDEX_op_st_i64, { "r", "r" } },
- { INDEX_op_add_i64, { "r", "0", "r" } },
- { INDEX_op_sub_i64, { "r", "0", "r" } },
+ { INDEX_op_add_i64, { "r", "0", "rI" } },
+ { INDEX_op_sub_i64, { "r", "0", "rNI" } },
{ INDEX_op_mul_i64, { "r", "0", "r" } },
{ INDEX_op_div2_i64, { "b", "a", "0", "1", "r" } },
--
1.7.0.1
