On Mon, Apr 4, 2016 at 7:14 PM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 4 April 2016 at 14:39, <vija...@caviumnetworks.com> wrote: >> From: Vijay <vija...@cavium.com> >> >> Set target page size to minimum 4K for aarch64. >> This helps to reduce live migration downtime significantly. >> >> Signed-off-by: Vijaya Kumar K <vija...@caviumnetworks.com> >> --- >> target-arm/cpu.h | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/target-arm/cpu.h b/target-arm/cpu.h >> index 066ff67..2e4b48f 100644 >> --- a/target-arm/cpu.h >> +++ b/target-arm/cpu.h >> @@ -1562,11 +1562,18 @@ bool write_cpustate_to_list(ARMCPU *cpu); >> #if defined(CONFIG_USER_ONLY) >> #define TARGET_PAGE_BITS 12 >> #else >> +/* >> + * Aarch64 support minimum 4K page size >> + */ >> +#if defined(TARGET_AARCH64) >> +#define TARGET_PAGE_BITS 12 > > I agree that this would definitely improve performance (both for > migration and for emulated guests), but I'm afraid this breaks > running 32-bit ARMv5 and ARMv7M guests with this QEMU binary, > so we can't do this. If we want to allow the minimum page size to > be bigger than 1K for AArch64 CPUs then we need to make it a > runtime settable thing rather than compile-time (which is not > an entirely trivial thing).
Do you mean to say that based on -cpu type qemu option choose the page size at runtime? > >> +#else >> /* The ARM MMU allows 1k pages. */ >> /* ??? Linux doesn't actually use these, and they're deprecated in recent >> architecture revisions. Maybe a configure option to disable them. */ >> #define TARGET_PAGE_BITS 10 >> #endif >> +#endif >> >> #if defined(TARGET_AARCH64) >> # define TARGET_PHYS_ADDR_SPACE_BITS 48 > > thanks > -- PMM
