This series implements the last piece of the minimal support required to boot MIPSr6 SMP Linux on multiple Virtual Processors. Essentially it adds RESET_BASE register to CM GCR which can be used by the guest to specify the reset exception base address for each VP.
It applies on top of GIC patches: https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg06223.html Thanks, Leon Leon Alrae (3): target-mips: add exception base to MIPS CPU hw/mips_cpc: make VP correctly start from the reset vector hw/mips_cmgcr: implement RESET_BASE register in CM GCR hw/misc/mips_cmgcr.c | 54 +++++++++++++++++++++++++++++++++++++++++++- hw/misc/mips_cpc.c | 5 ++-- include/hw/misc/mips_cmgcr.h | 18 +++++++++++++++ target-mips/cpu.h | 2 ++ target-mips/helper.c | 6 ++--- target-mips/translate.c | 9 +++++++- 6 files changed, 86 insertions(+), 8 deletions(-) -- 2.7.4
